5.01 Sequential Logic Fundamentals, Latches & Flip-Flops (SR & JK)

Digital logic systems are broadly classified into Combinational and Sequential systems. While combinational circuits produce outputs solely determined by current inputs, sequential logic circuits incorporate memory elements and feedback paths. This enables the circuit to store binary states, making output values dependent on both present inputs and historical execution states.

The most-asked question in Chapter 5 lives in this note

“Write down the characteristic table and excitation table of RS, JK, D and T flip-flop” has appeared eight times — 2015, 2016, 2017, 2018, 2019, 2020, 2021, 2022 — for 10–12 marks. See §6.

Close behind: “Why is a flip-flop called a one-bit memory element? Distinguish combinational and sequential circuits” — 2018, 2023, 2024, 2025 (§1), and the state table / diagram / equation definitions — 2015, 2016, 2021, 2022 (§2).

1. Combinational vs. Sequential Logic Systems

Exam Problem (PYQ 2018 — 10 marks; 2023 — 6+6; 2024 — 10; 2025 — 5+5)

Question (verbatim, 2024): Why flip-flop is called one bit memory element? Distinguish combinational circuit and sequential circuit.

The 6+6 and 5+5 splits tell you the two halves carry equal weight. For the first half: a flip-flop is bistable — it holds one of two stable states indefinitely without further input, and that retained state is exactly one bit of stored information. For the second, use the comparison table in §1.2.

1.1 Architectural Comparison

[Architectural diagrams for Combinational and Sequential Circuits]

1.2 Quantitative & Structural Differences

Feature	Combinational Circuit	Sequential Circuit [PYQ: 2023, 2024, 2025]
Output Dependency	Strictly function of Present Inputs X(t).	Function of Present Inputs X(t) AND Present State Q(t).
Memory Requirement	No memory elements present.	Requires Memory Elements (Latches or Flip-Flops).
Feedback Loop	Absent. Signals flow strictly input-to-output.	Present. Memory feedback path feeds present state Q(t) into logic.
Clock Synchronization	Asynchronous (no clock signal required).	Can be Synchronous (clocked) or Asynchronous.
Operating Speed	Faster (no storage element propagation delays).	Slower (governed by flip-flop delay tpd & clock period Tclk).
Design & Synthesis	K-map or Quine-McCluskey SOP/POS minimization.	State reduction, State assignment, Excitation table mapping.
Standard Building Blocks	Adders, Subtractors, Decoders, MUX, DEMUX.	Registers, Counters, RAM/ROM Memory, Shift Registers.

2. Fundamental Terminology & System Definitions

Definitions Question (PYQ 2015, 2016 — 08 marks; 2021, 2022 — 10 marks)

Question (verbatim, 2022): Define: State table, State diagram, State equation and Register.

The 2021 version adds a figure: “…An example of clocked sequential circuit is shown in figure 7(b). Obtain the state table of the sequential circuit.” — so the definitions come first, then an analysis worth most of the marks. See 5.04 Synchronous Sequential Circuit Analysis & Synthesis for the analysis procedure.

Only the 2022 paper includes Register in the list; 2015, 2016 and 2021 ask for the first three only.

Key Terminology

Flip-Flop (1-Bit Memory Element) [PYQ: 2018, 2023, 2024, 2025]: A bistable multivibrator capable of storing exactly one bit of binary data (0 or 1). It maintains its stored state indefinitely as long as power is supplied and no trigger pulse is applied.
State Table (Transition Table) [PYQ: 2015, 2016, 2021, 2022]: A tabular mapping showing Present State (Qn), External Inputs (X), Next State (Qn+1), and Present Outputs (Y).
State Diagram [PYQ: 2015, 2016, 2021, 2022]: A directed graph where nodes represent discrete states and directed arrows denote transitions labeled as Input / Output.
State Equation (Characteristic Equation) [PYQ: 2015, 2016, 2021]: An algebraic Boolean expression defining Qn+1 = f(Qn, Inputs).
Register [PYQ: 2015, 2016, 2021, 2022]: An array of N flip-flops clocked simultaneously to store an N-bit binary word.

3. Latches vs. Flip-Flops (Triggering Mechanics)

Characteristic	Latch	Flip-Flop
Triggering Method	Level-Triggered (Active HIGH or Active LOW Enable signal).	Edge-Triggered (Positive/Rising or Negative/Falling Clock Edge).
Response Window	Output continuously tracks inputs throughout active clock level.	Output changes strictly at the discrete instant of clock transition.
Noise & Glitch Sensitivity	High (vulnerable to input glitches while Enable is HIGH).	Low (immune to input variations except during setup/hold time).
Primary Use Case	Temporary asynchronous data buffers.	Synchronous sequential logic, shift registers, counters.

4. Set-Reset (SR) Latch Mechanics

An SR latch is an asynchronous bistable circuit with two inputs: Set (S) and Reset (R), and two complementary outputs (Q and Q’).

4.1 NOR Gate SR Latch Realization

[Logic diagram representation of NOR SR Latch]

Truth Table (NOR SR Latch) [PYQ: 2015, 2018]

S	R	Qn+1	Q’n+1	Operation / State
0	0	Qn	Q’n	No Change (Hold)
0	1	0	1	Reset
1	0	1	0	Set
1	1	0	0	Forbidden / Invalid State (Violates Q = Q’)

5. Clocked Flip-Flops: SR and JK

5.1 Clocked SR Flip-Flop

Adding clock-gating AND/NAND logic forces state transitions to occur only when CLK = 1.

Step-by-Step Derivation of SR Characteristic Equation [PYQ: 2015, 2017, 2021]

Characteristic Table:

S	R	Qn	Qn+1	Minterm
0	0	0	0	m0
0	0	1	1	m1
0	1	0	0	m2
0	1	1	0	m3
1	0	0	1	m4
1	0	1	1	m5
1	1	0	X	m6 (Don’t Care)
1	1	1	X	m7 (Don’t Care)

K-Map Optimization:

Grouping terms m1, m5 and m4, m5, m6, m7:

Qn+1 = S + R’Qn subject to S * R = 0

Exam Refinement Justification [PYQ: 2023, 2025]: In an SR flip-flop, S=1, R=1 results in an invalid/forbidden output state (Q=Q’=0). The JK Flip-Flop eliminates this illegal condition by feeding output lines Q and Q’ back to the input gates. When J=1, K=1, the circuit enters a deterministic Toggle state (Qn+1 = Qn’).

[Logic diagram representation of JK Flip-Flop with NAND gates]

Derivation of JK Characteristic Equation [PYQ: 2015, 2016, 2019, 2022]

Characteristic Table:

J	K	Qn	Qn+1	Operation
0	0	0	0	Hold
0	0	1	1	Hold
0	1	0	0	Reset
0	1	1	0	Reset
1	0	0	1	Set
1	0	1	1	Set
1	1	0	1	Toggle
1	1	1	0	Toggle

K-Map Optimization:

Grouping minterms m4, m5 (JQn’) and m1, m5 (K’Qn):

Qn+1 = JQn’ + K’Qn

The eight-appearance question — know all four tables cold

Question (verbatim, 2017/2018/2020/2021): Write down the characteristics table and excitation table of RS, JK, D and T flip-flop. (10 marks)

Variants: 2015 asks for excitation tables only (10); 2016 says “Draw the diagram of RS, JK, D and T flip-flop. From these diagrams write their characteristics tables and derive characteristics equations” (12) — the derivation is extra; 2019 asks for diagrams plus both tables (12); 2022 prints “execution table”, meaning excitation table (10).

The four characteristic equations to have memorised: $Q_{n + 1} = S + R^{'} Q_{n} (SR) Q_{n + 1} = J Q_{n}^{'} + K^{'} Q_{n} (JK)$ $Q_{n + 1} = D (D) Q_{n + 1} = T Q_{n}^{'} + T^{'} Q_{n} = T \oplus Q_{n} (T)$

The four excitation tables (what inputs produce a required transition):

$Q_{n} \to Q_{n + 1}$ $S R$ $J K$ $D$ $T$
$0 \to 0$ $0 \times$ $0 \times$ 0 0
$0 \to 1$ $10$ $1 \times$ 1 1
$1 \to 0$ $01$ $\times 1$ 0 1
$1 \to 1$ $\times 0$ $\times 0$ 1 0

Do not confuse the two table types. The characteristic table maps inputs → next state (used for analysis). The excitation table maps a required state change → the inputs needed (used for design — every counter and sequential-circuit question in Chapters 5 and 6 depends on it).

$Q_{n} \to Q_{n + 1}$	$S R$	$J K$	$D$	$T$
$0 \to 0$	$0 \times$	$0 \times$	0	0
$0 \to 1$	$10$	$1 \times$	1	1
$1 \to 0$	$01$	$\times 1$	0	1
$1 \to 1$	$\times 0$	$\times 0$	1	0

Excitation Table (JK Flip-Flop)

Qn	Qn+1	Required J	Required K
0	0	0	X
0	1	1	X
1	0	X	1
1	1	X	0

6. Key Exam Traps & Warning Checkpoints

SR Equation Constraint: Always write subject to S * R = 0 alongside Qn+1 = S + R’Qn. Omitting the constraint loses 1-2 marks.
NOR Latch Connections: In a NOR-gate SR latch, S=1 sets Q=1, but the S line physically connects to the lower NOR gate whose output is Q.
JK Refinement Proof: When asked why JK is a refinement of RS, explicitly show that for J=K=1: Qn+1 = (1)Qn’ + (0)Qn = Qn’. This replaces the illegal state with a deterministic Toggle state, proving that JK is the refinement of RS.

7. Past Year Questions (PYQs)

PYQ Index for this note

Question (as asked) Years Marks Solved in
Write down the characteristic table and excitation table of RS, JK, D and T flip-flop 2017, 2018, 2020, 2021, 2022 10 §5
Write down the excitation table of RS, D, JK and T flip-flop 2015 10 §5
Draw the diagram of RS, JK, D and T flip-flop; write characteristic tables and derive characteristic equations 2016 12 §5
Draw the diagram of RS, JK, D and T flip-flop; also write characteristic and excitation tables 2019 12 §5
What is flip-flop? Why is flip-flop called one-bit memory cell? 2018 10 §1
Why is flip-flop called one bit memory element? Distinguish combinational and sequential circuit 2023 (6+6), 2024 (10), 2025 (5+5) 10–12 §1
Define state table, state diagram and state equation 2015, 2016 8 §2
Define: state table, state diagram, state equation and register 2022 10 §2
For a JK flip-flop obtain (i) characteristic table, (ii) characteristic equation, (iii) excitation table, (iv) show that tying the two external inputs together forms a D flip-flop 2024 13 §5, and 5.03 Flip-Flop Conversions & Functional Transformation Mechanics
”JK flip-flop is the refinement of RS flip-flop” — justify 2023 (11), 2025 (09) 9–11 §5

Pattern to notice: the flip-flop tables question appears in eight of the last eleven papers and is worth 10–12 marks of pure recall — the single most reliable item in Chapter 5. Everything else in this note is asked as a short definition attached to a longer question.

The 2024 twist: part (iv) — “show that tying the two external inputs together forms a D flip-flop” — is a conversion question grafted onto the tables question. Tying $J = K = T$ gives a T flip-flop; tying $J = D$ and $K = D^{'}$ gives a D flip-flop. Read which one is being asked.

Question (as asked)	Years	Marks	Solved in
Write down the characteristic table and excitation table of RS, JK, D and T flip-flop	2017, 2018, 2020, 2021, 2022	10	§5
Write down the excitation table of RS, D, JK and T flip-flop	2015	10	§5
Draw the diagram of RS, JK, D and T flip-flop; write characteristic tables and derive characteristic equations	2016	12	§5
Draw the diagram of RS, JK, D and T flip-flop; also write characteristic and excitation tables	2019	12	§5
What is flip-flop? Why is flip-flop called one-bit memory cell?	2018	10	§1
Why is flip-flop called one bit memory element? Distinguish combinational and sequential circuit	2023 (6+6), 2024 (10), 2025 (5+5)	10–12	§1
Define state table, state diagram and state equation	2015, 2016	8	§2
Define: state table, state diagram, state equation and register	2022	10	§2
For a JK flip-flop obtain (i) characteristic table, (ii) characteristic equation, (iii) excitation table, (iv) show that tying the two external inputs together forms a D flip-flop	2024	13	§5, and 5.03 Flip-Flop Conversions & Functional Transformation Mechanics
”JK flip-flop is the refinement of RS flip-flop” — justify	2023 (11), 2025 (09)	9–11	§5

8. Legacy Worked Questions

PYQ Master Problem (2023, 2025): Refinement Justification

Question: “JK flip-flop is the refinement of RS flip-flop” — Justify the statement with necessary logic diagrams and truth tables. [6 Marks]

Solution:

Identification of RS Latch Limitation: In an RS flip-flop, when S=1 and R=1 are applied simultaneously, both NOR outputs are forced to 0 (Q=Q’=0), which violates the fundamental complementary property Q = Q’. When inputs return to 0, the final state is unpredictable (race condition).
Feedback Modification in JK: The JK flip-flop modifies the RS architecture by introducing cross-coupled feedback: S = J * Q’ and R = K * Q.
Mathematical Proof of Deterministic Toggle: Substitute J=1, K=1 into the derived characteristic equation Qn+1 = JQn’ + K’Qn: Qn+1 = 1 * Qn’ + 0 * Qn = Qn’. This replaces the illegal state with a deterministic Toggle state, proving that JK is the refinement of RS.

007_index

5.01 Sequential Logic Fundamentals, Latches & Flip-Flops (SR & JK)

5.01 Sequential Logic Fundamentals, Latches & Flip-Flops (SR & JK)

1. Combinational vs. Sequential Logic Systems

1.1 Architectural Comparison

1.2 Quantitative & Structural Differences

2. Fundamental Terminology & System Definitions

3. Latches vs. Flip-Flops (Triggering Mechanics)

4. Set-Reset (SR) Latch Mechanics

4.1 NOR Gate SR Latch Realization

5. Clocked Flip-Flops: SR and JK

5.1 Clocked SR Flip-Flop

5.2 Clocked JK Flip-Flop & Refinement Proof

6. Key Exam Traps & Warning Checkpoints

7. Past Year Questions (PYQs)

8. Legacy Worked Questions

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