Related Concepts: 5.01 Sequential Logic Fundamentals, Latches & Flip-Flops (SR & JK) | 6.02 Asynchronous (Ripple) Counters & Propagation Delay Calculations | 6.04 Specialized Counters (Up-Down, Johnson, Ring & Mod-N ICs)

6.01 Registers, Parallel Load & Shift Register Dynamics

Two near-certain questions live in this note

Question	Appearances	Marks
Shift register tracking numerical	7 (2017, 2018, 2020, 2021, 2023, 2024, 2025)	10–12
4-bit register with parallel load using D flip-flops	6 (2015, 2016, 2017, 2021, 2023, 2025)	10–15

Together roughly 20–25 marks per paper. The tracking numerical needs no theory at all — just a carefully filled table.

Overview

A Register is a digital circuit constructed from a cascading array of N flip-flops operating under a common clock signal. While a single flip-flop stores 1 bit of data, an N-bit register stores an N-bit binary word. Registers serve as the fundamental data-storage and data-movement components inside microprocessors and digital signal processors.

1. 4-Bit Register with Parallel Load

Major Exam Problem (PYQ 2015 — 15 marks; 2017 — 12 marks; 2016, 2021 — 10 marks; 2023, 2025 — 3+7 marks)

Question (verbatim, 2023/2025): What is register? Draw the diagram of a 4-bit register with parallel load using D flip-flop.

The 2015 and 2017 papers add “and explain its operation”, and 2021 says “and external gates” — i.e. draw the steering logic explicitly rather than hiding it inside a MUX symbol. The 3+7 split in 2023/2025 tells you exactly how to budget: about 3 marks for the definition, 7 for the diagram.

Definition to open with: A register is a group of $N$ flip-flops sharing a common clock, capable of storing an $N$-bit binary word.

In a basic register without control gating, new data is loaded at every clock edge. To retain stored data across multiple clock cycles, a Parallel Load Control Signal (Load) is added using 2-to-1 Multiplexers (or steering AND-OR logic) at each flip-flop input.

1.1 Steering Logic & Circuit Operation

For each bit i (i = 0, 1, 2, 3):

• When Load = 1: The 2x1 MUX selects external input Ii. On the next active clock edge, Ai ← Ii (New Data Loaded).
• When Load = 0: The 2x1 MUX selects the present output Ai. On the next active clock edge, Ai ← Ai (Data Retained / Held).

Di = Load · Ii + Load’ · Ai

 Load Line

|

v

I_i -⇒[ 1 ]

[ MUX ]---⇒ D_i -⇒[ D FLIP-FLOP ]---⇒ A_i (Output)

A_i -⇒[ 0 ] |

CLK

2. Serial Transfer vs. Parallel Transfer

Exam Problem (PYQ 2018 — 07 marks)

Question (verbatim): What is the difference between serial and parallel transfer? What type of register is used in each case?

Answer both halves — the second clause is worth roughly a third of the marks: shift registers for serial transfer, parallel-load registers for parallel transfer.

Digital data can be transferred between registers using two fundamental modes:

Feature	Serial Transfer	Parallel Transfer
Data Transmission Method	Bits are transferred one bit at a time sequentially over a single wire.	All N bits are transferred simultaneously over N parallel data lines.
Hardware Complexity	Low. Requires only 1 physical transmission line.	High. Requires N separate data lines and complex bus routing.
Transfer Time (Speed)	Slow. Requires N clock pulses to transfer an N-bit word.	Fast. Requires 1 clock pulse regardless of word length N.
Primary Register Type	Shift Registers (SISO, SIPO).	Parallel-Load Registers (PIPO).
Application Examples	Long-distance communication (USB, SPI, UART).	Internal CPU bus transfers (ALU to Accumulator).

3. Shift Register Classification

A Shift Register is a register capable of shifting stored binary data left or right by one bit position during each clock transition.

1. SISO (Serial-In, Serial-Out): Data entered serially, retrieved serially (N clock cycles for load, N for output).
2. SIPO (Serial-In, Parallel-Out): Data entered serially, retrieved simultaneously across parallel output pins.
3. PISO (Parallel-In, Serial-Out): Data loaded simultaneously in parallel, shifted out serially.
4. PIPO (Parallel-In, Parallel-Out): Data loaded simultaneously and retrieved simultaneously.

4. Shift Register Tracking Numericals

Seven appearances — the most repeated numerical in Chapter 6

2017, 2018, 2020, 2021, 2023, 2024, 2025, worth 10–12 marks. Only three variants have ever been set, and all three are worked below. The question is always fully specified in the text — no figure needed.

The Shift-Right Rule

For a register $A_3{A}_2{A}_1{A}_0$ shifted right by one position:

$A_3\leftarrow \text{Serial Input},A_2\leftarrow A_3,A_1\leftarrow A_2,A_0\leftarrow A_1$

and the old $A_0$ is shifted out. Serial input bits are consumed left to right from the given string, one per clock pulse.

4.1 Variant A — 4-bit, six shifts

Worked Exam Problem (PYQ 2017, 2021 — 10 marks; 2018 — 12 marks)

Question (verbatim): The content of a 4-bit shift register is initially 1101. The register is shifted six times to the right with the serial input being 101101. What is the content of the register after each shift?

Shift	Serial in	$A_3$	$A_2$	$A_1$	$A_0$	Register	Bit shifted out
Initial	—	1	1	0	1	1101	—
1	1	1	1	1	0	1110	1
2	0	0	1	1	1	0111	0
3	1	1	0	1	1	1011	1
4	1	1	1	0	1	1101	1
5	0	0	1	1	0	0110	1
6	1	1	0	1	1	1011	0

Final content after 6 shifts: 1011

4.2 Variant B — 4-bit, seven shifts

Worked Exam Problem (PYQ 2023 — 12 marks; 2025 — 10 marks)

Question (verbatim): The content of a 4-bit shift register is initially 1011. The register is shifted seven times to right with serial input 1011011. What will be the content of the register after each shift?

Shift	Serial in	Register
Initial	—	1011
1	1	1101
2	0	0110
3	1	1011
4	1	1101
5	0	0110
6	1	1011
7	1	1101

Final content after 7 shifts: 1101

4.3 Variant C — 5-bit, six shifts

Worked Exam Problem (PYQ 2020, 2024 — 10 marks)

Question (verbatim): The content of a 5-bit shift register is initially 10110. The register is shifted six times to right with serial input 101100. What will be the content of the register after each shift?

Shift	Serial in	Register $A_4{A}_3{A}_2{A}_1{A}_0$
Initial	—	10110
1	1	11011
2	0	01101
3	1	10110
4	1	11011
5	0	01101
6	0	00110

Final content after 6 shifts: 00110

How to not lose marks on a question you already know

• Show every intermediate row. The question says “after each shift” — the table is the answer. A final value alone scores a fraction of the marks.
• Consume the serial input left to right, one bit per shift. Count the bits in the given string: it always matches the stated number of shifts exactly (six shifts ↔ six input bits). If they don’t match, you have misread the question.
• Shift right means toward the LSB. New bits enter at $A_3$ (the MSB end) and leave from $A_0$.
• Watch the period. In Variants A and B the pattern repeats every 3 shifts — a useful self-check, since row 4 should equal row 1’s successor pattern.

5. Cascaded Shift Registers Tracking

Exam Problem (PYQ 2016 — 10 marks; 2019, 2022 — 12 marks)

Question (verbatim, 2019): The content of the shift register A and B is 1011 and 1101 as shown in figure 7(b). What will be the content of each register after 6 clock pulses? Show the result for each clock pulse.

(2016 uses A = 1101 with B initially cleared; 2022 repeats the 2019 values.)

This question depends on a figure — establish the topology first

Unlike §4, these problems reference Fig. 7(b), and the answer depends entirely on how the two registers are wired. The two common arrangements are:

• Cascade (open chain): $A$‘s serial output feeds $B$‘s serial input; $A$ receives a fixed serial input (often 0). After $N$ pulses, $A$‘s contents have migrated into $B$.
• Circulating (closed loop): $A_0\to B$‘s input and $B_0\to A$‘s input. Nothing is lost; the combined 8-bit pattern simply rotates, returning to its start after 8 pulses.

Check the arrow directions in the figure before computing anything. An answer worked with the wrong topology is wrong from pulse 1.

The Method

Whatever the topology, build one table with a column per register and one row per clock pulse:

1. Write the initial contents of both registers.
2. For each pulse, determine each register’s serial input — read it off the figure, using the pre-shift value of whichever bit feeds it.
3. Shift both registers simultaneously using the rule in §4.
4. Repeat for the stated number of pulses.

The step that trips people

Both registers shift on the same clock edge, so both serial inputs must be read from the values that existed before that edge. Updating register $A$ first and then feeding its new $A_0$ into $B$ produces an answer that is one pulse out of step — the most common error in this question.

Self-check for the circulating case: the multiset of 1s across both registers never changes, since no bit is lost. If your bit count drifts, you have made an arithmetic slip.

A fully worked version requires Fig. 7(b) from the question paper — reconstruct the wiring from your copy, then apply the table method above.