6.06 Register Architectures, Parallel Load & Shift Register Topologies

aliases:

• Registers vs Counters Matrix
• 4-Bit Parallel Load Register Schematic
• Shift Register Topologies (SISO, SIPO, PISO, PIPO)
• Shift Register Content Tracker
• 12-Bit Register Content Decoding

tags:

• digital-electronics
• ece-2103
• term-2-1
• study-order/6.06

type: uni-note

course: “ECE 2103 - Digital Electronics and Logic Circuits”

chapter_map: “06 Chapter Map - Registers & Counters”

term: 2-1

teacher: Foysal Sir

status: enhanced

Related Concepts: 6.01 Registers, Parallel Load & Shift Register Dynamics | 6.02 Asynchronous (Ripple) Counters & Propagation Delay Calculations | 6.05 Chapter 6 Master PYQ Solutions & Counter Puzzles

6.06 Register Architectures, Parallel Load & Shift Register Topologies

Overview Registers store and manipulate multi-bit binary data. Understanding parallel load steering logic, shift register topologies (SISO, SIPO, PISO, PIPO), serial tracking numericals, and multi-code register decoding is essential for digital system design.

1. Registers vs. Counters Comparison Matrix

Feature	Register	Counter
Primary Function	Storing and transferring multi-bit data words.	Tracking and counting pulse sequences / events.
State Sequence	Arbitrary (depends on external data input).	Deterministic cyclic sequence ($0,1,2,\dots ,N$).
Clocking	All flip-flops clocked simultaneously.	Can be Asynchronous (Ripple) or Synchronous.
Primary Building Block	Parallel-load or Shift Registers.	Synchronous / Asynchronous Counters.

2. 4-Bit Parallel Load Register Architecture [PYQ: 2015, 2016, 2017, 2021, 2023, 2025]

To prevent stored data from being overwritten on every clock edge, a Parallel Load Line ($Load$) controls 2-to-1 MUXes at each D flip-flop input.

 Load Line

|

v

I_i -⇒[ 1 ]

[ MUX ]---⇒ D_i -⇒[ D FLIP-FLOP ]---⇒ A_i (Output)

A_i -⇒[ 0 ] |

CLK

2.1 Boolean Input Equation

$D\_i=Load\cdot I\_i+\overline{Load}\cdot A\_i$

3. Shift Register Topologies & Use-Cases

1. SISO (Serial-In, Serial-Out): Used for time-delay generation and long-distance serial data links.
2. SIPO (Serial-In, Parallel-Out): Converts serial data streams into parallel words (e.g., UART receivers).
3. PISO (Parallel-In, Serial-Out): Converts parallel bus words into serial bitstreams (e.g., UART transmitters).
4. PIPO (Parallel-In, Parallel-Out): Temporary internal CPU registers (e.g., Accumulator, Instruction Register).

4. Shift Register Content Tracker Tutorial [PYQ: 2017–2025]

4.1 4-Bit Right Shift Example

• Initial Content: $A\_3A\_2A\_1A\_0=1101$.
• Serial Input Stream: 101101 (applied LSB first).

Pulse	Serial In	$A\_3$	$A\_2$	$A\_1$	$A\_0$	Serial Output
0	—	1	1	0	1	—
1	1	1	1	1	0	1
2	0	0	1	1	1	0
3	1	1	0	1	1	1
4	1	1	1	0	1	1

5. 12-Bit Register Multi-Code Decoding Puzzle [PYQ: 2022]

Register State: 100010010111 (Nibbles: 1000, 1001, 0111).

• BCD Code: 1000=8, 1001=9, 0111=7 $⟹$ 897.
• Excess-3 Code: Subtract 3: 8-3=5, 9-3=6, 7-3=4 $⟹$ 564.
• 8, 4, -2, -1 Code: $8(1)+4(0)-2(0)-1(0)=8$, $8(1)-1(1)=7$, $4(1)-2(1)-1(1)=1⟹$ 871.
• Binary Integer: $100010010111\_2=2199\_10$.