06 Chapter Map - Registers & Counters
Chapter 6 Overview & Map of Content (MOC)
Multi-bit storage registers, parallel load mechanics, shift register tracking, asynchronous ripple counters and propagation delay, synchronous counter design (irregular sequences, 84-2-1, Excess-3, BCD), up-down counters, Ring and Johnson counters, and parallel-load counter ICs.
📚 Study Notes Index
| # | Note | What it covers | PYQ years | Typical marks |
|---|---|---|---|---|
| 6.01 | 6.01 Registers, Parallel Load & Shift Register Dynamics | Shift register tracking, parallel-load register, serial vs parallel transfer, SISO/SIPO/PISO/PIPO | 2015–2025 (most papers) | 7–15 |
| 6.02 | 6.02 Asynchronous (Ripple) Counters & Propagation Delay Calculations | Ripple counter definition, delay and , truncated counters | 2018 | 13 |
| 6.03 | 6.03 Synchronous Counter Design (Sequence, Code & BCD Counters) | Irregular sequence counters, 84-2-1 counter, Excess-3 counter, BCD counter | every paper | 10–15 |
| 6.04 | 6.04 Specialized Counters (Up-Down, Johnson, Ring & Mod-N ICs) | Up-down counter, Johnson counter, ring counter, Mod-N with parallel load | 2015, 2017–2019, 2021–2023, 2025 | 5–13 |
| 6.05 | 6.05 Chapter 6 Master PYQ Solutions & Counter Puzzles | Additional worked counter problems | — | — |
🎯 Exam Weight
Every paper contains at least two questions from this chapter
Rank Question Appearances Marks Note 1 Shift register tracking numerical 7 10–12 6.01 Registers, Parallel Load & Shift Register Dynamics §4 1 Irregular sequence counter (15-10-9-…) 7 10–15 6.03 Synchronous Counter Design (Sequence, Code & BCD Counters) §3 3 4-bit register with parallel load 6 10–15 6.01 Registers, Parallel Load & Shift Register Dynamics §1 4 4-bit synchronous up-down counter 5 5–10 6.04 Specialized Counters (Up-Down, Johnson, Ring & Mod-N ICs) §1 5 Excess-3 code counter 4 10–13 6.03 Synchronous Counter Design (Sequence, Code & BCD Counters) §5 5 Johnson counter, 10 timing signals 4 9–10 6.04 Specialized Counters (Up-Down, Johnson, Ring & Mod-N ICs) §4 7 84-2-1 code counter 3 10–12 6.03 Synchronous Counter Design (Sequence, Code & BCD Counters) §4 7 Cascaded shift registers 3 10–12 6.01 Registers, Parallel Load & Shift Register Dynamics §5 Roughly 30–40 marks per paper. The shift-register tracking numerical is the single cheapest — no theory, just a carefully filled table, and only three variants have ever been set.
One procedure covers every counter question
Flip-flop count → state/excitation table → K-maps with unused states as don’t cares → verify by substitution → draw the circuit.
The only variables between years are the sequence and the flip-flop type (JK or T). Check both before starting — using the wrong excitation table makes everything from step 2 onward wrong.
Recurring traps in this chapter
- Flip-flop type changes by year. Sequence counters: JK in 2015, 2016, 2020, 2022; T in 2023, 2024, 2025. Excess-3: T in 2019, 2022; JK in 2024, 2025.
- 84-2-1 is not binary order. Decimal 4 → 5 is
0100→1011; every bit flips. Write the code table first.- Johnson decoding needs one complement per term. , not — otherwise each gate fires in two states.
- Up-down steering needs primes on the down-path. , not .
- Synchronous LOAD vs asynchronous CLEAR decide which state you decode for Mod-N: for load, for clear.
- Cascaded shift registers depend on a figure. Establish whether it is an open chain or a circulating loop before computing anything.
🔗 Related Resources
- Course Teaching Plan: ECE 2103 - Digital Electronics and Logic Circuits
- Instructor: Foysal Sir (Instructor 2), Weeks 5–7
- Previous chapter: 05 Chapter Map - Sequential Logic & Flip-Flops — flip-flop excitation tables, the foundation of every counter design here
- Next chapter: 07 Chapter Map - Multivibrators, Memory & Converters
- Lab tie-in (ECE 2104): Week 7 builds a 4-bit ripple counter; Week 8 a 4-bit shift register.