Chapter 6 - Registers & Counters

06 Chapter Map - Registers & Counters

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title: “06 Chapter Map - Registers & Counters”

aliases:

• Chapter 6 Map

• Chapter 6 MOC

tags:

• digital-electronics

• ece-2103

• term-2-1

• map-of-content

type: MOC

course: “ECE 2103 - Digital Electronics and Logic Circuits”

chapter: 6

term: 2-1

teacher: Foysal Sir

status: enhanced

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06 Chapter Map - Registers & Counters

[!abstract] Chapter 6 Overview & Map of Content (MOC)

Multi-bit storage registers, parallel load mechanics, shift register tracking, asynchronous ripple counters, propagation delay calculations, synchronous counter design (irregular sequences, 84-2-1 code, Excess-3 code, BCD), up-down counters, Ring & Johnson counters, and parallel-load counter ICs.

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📚 Study Notes Index

• 6.01 Registers, Parallel Load & Shift Register Dynamics

• 6.02 Asynchronous (Ripple) Counters & Propagation Delay Calculations

• 6.03 Synchronous Counter Design (Sequence, Code & BCD Counters)

• 6.04 Specialized Counters (Up-Down, Johnson, Ring & Mod-N ICs)

• 6.05 Chapter 6 Master PYQ Solutions & Counter Puzzles

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🔗 Related Resources

• Course Teaching Plan: ECE 2103 - Digital Electronics and Logic Circuits

• Instructor: Foysal Sir (Instructor 2)

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6.01 Registers, Parallel Load & Shift Register Dynamics

Related Concepts: 5.01 Sequential Logic Fundamentals, Latches & Flip-Flops (SR & JK) | 6.02 Asynchronous (Ripple) Counters & Propagation Delay Calculations | 6.04 Specialized Counters (Up-Down, Johnson, Ring & Mod-N ICs)

6.01 Registers, Parallel Load & Shift Register Dynamics

Overview

A Register is a digital circuit constructed from a cascading array of N flip-flops operating under a common clock signal. While a single flip-flop stores 1 bit of data, an N-bit register stores an N-bit binary word. Registers serve as the fundamental data-storage and data-movement components inside microprocessors and digital signal processors.

1. 4-Bit Register with Parallel Load [PYQ: 2015, 2016, 2017, 2021, 2023, 2025]

In a basic register without control gating, new data is loaded at every clock edge. To retain stored data across multiple clock cycles, a Parallel Load Control Signal (Load) is added using 2-to-1 Multiplexers (or steering AND-OR logic) at each flip-flop input.

1.1 Steering Logic & Circuit Operation

For each bit i (i = 0, 1, 2, 3):

• When Load = 1: The 2x1 MUX selects external input Ii. On the next active clock edge, Ai ← Ii (New Data Loaded).
• When Load = 0: The 2x1 MUX selects the present output Ai. On the next active clock edge, Ai ← Ai (Data Retained / Held).

Di = Load · Ii + Load’ · Ai

 Load Line

|

v

I_i -⇒[ 1 ]

[ MUX ]---⇒ D_i -⇒[ D FLIP-FLOP ]---⇒ A_i (Output)

A_i -⇒[ 0 ] |

CLK

2. Serial Transfer vs. Parallel Transfer [PYQ: 2018]

Digital data can be transferred between registers using two fundamental modes:

Feature	Serial Transfer	Parallel Transfer
Data Transmission Method	Bits are transferred one bit at a time sequentially over a single wire.	All N bits are transferred simultaneously over N parallel data lines.
Hardware Complexity	Low. Requires only 1 physical transmission line.	High. Requires N separate data lines and complex bus routing.
Transfer Time (Speed)	Slow. Requires N clock pulses to transfer an N-bit word.	Fast. Requires 1 clock pulse regardless of word length N.
Primary Register Type	Shift Registers (SISO, SIPO).	Parallel-Load Registers (PIPO).
Application Examples	Long-distance communication (USB, SPI, UART).	Internal CPU bus transfers (ALU to Accumulator).

3. Shift Register Classification

A Shift Register is a register capable of shifting stored binary data left or right by one bit position during each clock transition.

1. SISO (Serial-In, Serial-Out): Data entered serially, retrieved serially (N clock cycles for load, N for output).
2. SIPO (Serial-In, Parallel-Out): Data entered serially, retrieved simultaneously across parallel output pins.
3. PISO (Parallel-In, Serial-Out): Data loaded simultaneously in parallel, shifted out serially.
4. PIPO (Parallel-In, Parallel-Out): Data loaded simultaneously and retrieved simultaneously.

4. Shift Register Tracking Numericals [PYQ: Heavily Tested: 2017–2025]

PYQ Master Problem (2017, 2021, 2024): 4-Bit Serial Shift Tracking

Question: A 4-bit shift register is initially loaded with the binary string 1101. Serial input data stream 1011 is applied to the serial input pin (LSB first). Determine the register contents after each shift. [6 Marks]

Solution Methodology:

Let initial register content be A3 A2 A1 A0 = 1101. Shifting right means: A3 ← Serial Input, A2 ← A3, A1 ← A2, A0 ← A1. Serial Input Sequence (LSB first): 1 (1st shift), 1 (2nd shift), 0 (3rd shift), 1 (4th shift).

Clock Pulse	Serial Input Bit	A3	A2	A1	A0	Serial Output (A0)
Initial	—	1	1	0	1	—
Pulse 1	1	1	1	1	0	1
Pulse 2	1	1	1	1	1	0
Pulse 3	0	0	1	1	1	1
Pulse 4	1	1	0	1	1	1

Final Register Content after 4 shifts: 1011

5. Cascaded Shift Registers Tracking [PYQ: 2016, 2019, 2022]

When Register A is cascaded into Register B, the serial output A0 of Register A acts as the serial input to Register B.

PYQ Master Problem (2019): Cascaded 4-Bit Shift Registers

Question: Two 4-bit shift registers A and B are cascaded. Initial contents are A = 1011 and B = 0100. Register A receives a constant serial input of 0. Determine the contents of both registers after 4 clock pulses. [8 Marks]

Solution Table:

Clock Pulse	A Serial In	A3 A2 A1 A0	B Serial In (A0)	B3 B2 B1 B0
Initial	—	1011	—	0100
Pulse 1	0	0101	1	1010
Pulse 2	0	0010	1	1101
Pulse 3	0	0001	0	0110
Pulse 4	0	0000	1	1011

Final Contents after 4 Pulses: A = 0000, B = 1011 (Register A’s original data 1011 has been completely transferred into Register B).

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6.02 Asynchronous (Ripple) Counters & Propagation Delay Calculations

Related Concepts: 6.01 Registers, Parallel Load & Shift Register Dynamics | 6.03 Synchronous Counter Design (Sequence, Code & BCD Counters) | 6.04 Specialized Counters (Up-Down, Johnson, Ring & Mod-N ICs)

6.02 Asynchronous (Ripple) Counters & Propagation Delay Calculations

Overview: An Asynchronous Counter (commonly known as a Ripple Counter) is a sequential counting circuit where flip-flops are not clocked simultaneously. Instead, only the first flip-flop (LSB) receives the external system clock; each subsequent flip-flop is clocked by the output transition of the preceding flip-flop.

1. 4-Bit Binary Ripple Up-Counter [PYQ: 2018, 2022, 2023, 2025]

A 4-bit binary ripple up-counter counts sequentially from 0000₂ (0₁₀) to 1111₂ (15₁₀) using 4 negative-edge triggered JK flip-flops set to Toggle mode (J = K = 1).

1.1 Circuit Diagram & Connection Rules

 System CLK —⇒(CLK) [ FF 0 ]---⇒ Q0 (LSB)

|

(CLK) [ FF 1 ]---⇒ Q1

|

(CLK) [ FF 2 ]---⇒ Q2

|

(CLK) [ FF 3 ]---⇒ Q3 (MSB)

Connection Rule for Up-Counter vs. Down-Counter: • Up-Counter (Negative-Edge FFs): Connect Qᵢ to CLKᵢ₊₁. • Down-Counter (Negative-Edge FFs): Connect Q̅ᵢ to CLKᵢ₊₁.

2. Propagation Delay & Maximum Operating Frequency [PYQ: 2018]

Because transitions ripple sequentially through the cascade of N flip-flops, the total time required for a state update to settle across the entire counter is cumulative.

2.1 Mathematical Formulas

1. Total Cumulative Propagation Delay (t_total): For an N-bit ripple counter where each flip-flop has a propagation delay t_pd: t_total = N × t_pd

2. Maximum Operating Frequency (f_max): To ensure reliable operation without output corruption before settling: f_max = 1 / t_total = 1 / (N × t_pd)

PYQ Master Problem (2018): Maximum Frequency Calculation Question: A 10-bit ripple counter is constructed using flip-flops that each have a propagation delay of t_pd = 20 ns. Calculate: (i) The total propagation delay of the counter, (ii) The maximum clock frequency f_max at which the counter can operate reliably. [6 Marks] Solution:

1. Given: Number of bits N = 10, Propagation delay per flip-flop t_pd = 20 ns = 20 × 10⁻⁹ s.
2. Total Delay (t_total): t_total = N × t_pd = 10 × (20 ns) = 200 ns
3. Maximum Operating Frequency (f_max): f_max = 1 / t_total = 1 / (200 × 10⁻⁹ s) = 5 × 10⁶ Hz = 5 MHz

3. Truncated Ripple Counters (MOD-N / Decade Counter)

A full N-bit counter has a natural modulus of 2ᴺ. A Truncated Counter resets to 0000 before reaching 2ᴺ - 1 by decoding a specific terminal state using a feedback NAND gate connected to the asynchronous CLR̅ (Clear) inputs.

3.1 Design of a BCD / Decade Ripple Counter (MOD-10)

To count from 0000 (0) to 1001 (9) and reset at 1010 (10):

1. Target Terminal Count: 10₁₀ = 1010₂ (Q₃ Q₂ Q₁ Q₀ = 1010).

2. NAND Decoding Logic: Decode Q₃ = 1 and Q₁ = 1: CLR̅ = ̅(Q₃ · Q₁)

3. Operation: As soon as state 1010 (10) is momentarily reached, the NAND output drops to 0, asynchronously clearing all 4 flip-flops back to 0000 in a fraction of a nanosecond.

 Q3 -----\

[ NAND ]---⇒ Active-LOW Clear (CLR) to all 4 Flip-Flops

Q1 -----/



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6.03 Synchronous Counter Design (Sequence, Code & BCD Counters)

Related Concepts: 6.01 Registers, Parallel Load & Shift Register Dynamics | 6.02 Asynchronous (Ripple) Counters & Propagation Delay Calculations | 6.04 Specialized Counters (Up-Down, Johnson, Ring & Mod-N ICs)

In a Synchronous Counter, the clock input is connected directly to the clock terminals of all flip-flops simultaneously. This eliminates cumulative propagation delay, allowing synchronous counters to operate at much higher clock frequencies than ripple counters.

1. Asynchronous vs. Synchronous Counter Comparison

Feature	Asynchronous (Ripple) Counter	Synchronous Counter
Clock Signal Connection	Only 1st FF is clocked externally; subsequent FFs clocked by preceding FF outputs.	All FFs clocked simultaneously by the master system clock.
Propagation Delay	Cumulative (t_total = N x t_pd). Grows linearly with bit count N.	Fixed (t_total = t_pd + t_gate). Independent of bit count N.
Maximum Frequency	Low (f_max = 1 / (N * t_pd)).	High (f_max = 1 / (t_pd + t_gate)).
Glitch Susceptibility	High (transient decoding errors occur during rippling).	Low (state transitions settle simultaneously).
Design Flexibility	Limited to straight binary or simple truncated counters.	Unlimited. Can count any arbitrary sequence or non-weighted code.

2. Systematic Synchronous Counter Synthesis Procedure

1. Step 1: Determine Required Number of Flip-Flops N = ceil(log2 M)
2. Step 2: Construct Combined State & Excitation Table
3. Step 3: Minimize Flip-Flop Input Logic using K-Maps
4. Step 4: Draw Final Synchronous Circuit Schematic

3. Design Example 1: Irregular Sequence Counter [PYQ: Heavily Tested: 2015–2025]

PYQ Master Problem (2020, 2023, 2025): Sequence Counter

Question: Design a synchronous counter that counts the sequence 0 → 2 → 3 → 5 → 7 → 0 using T flip-flops. [10 Marks]

Solution:

1. Bit Count: Max value = 7_10 = 111_2 ⇒ N = 3 T flip-flops (C, B, A). Unused states: 1, 4, 6 (Don’t Cares).
2. State & Excitation Table (T FF Excitation: T = Q_n XOR Q_n+1):

Present State (C B A)	Next State (Cn+1 Bn+1 An+1)	TC	TB	TA
0 0 0 (0)	0 1 0 (2)	0	1	0
0 0 1 (1)	X X X (Unused)	X	X	X
0 1 0 (2)	0 1 1 (3)	0	0	1
0 1 1 (3)	1 0 1 (5)	1	1	0
1 0 0 (4)	X X X (Unused)	X	X	X
1 0 1 (5)	1 1 1 (7)	0	1	0
1 1 0 (6)	X X X (Unused)	X	X	X
1 1 1 (7)	0 0 0 (0)	1	1	1

1. K-Map Minimization for TC, TB, TA:
   1. TC = B * A
   2. TB = !C * !A + B * A = !C!A + BA
   3. TA = !C * B + C * B * A = B(!C + A)

4. Design Example 2: Code Counter in 84-2-1 Code [PYQ: 2016, 2017, 2020]

PYQ Master Problem (2017, 2020): 84-2-1 Code Counter

Question: Design a synchronous counter that counts decimal digits 0 to 9 according to the 84-2-1 code using T flip-flops. [10 Marks]

Solution Summary:

1. 84-2-1 Code Mapping: Decimal 0 = 0000, 1 = 0111, 2 = 0110, 3 = 0101, 4 = 0100, 5 = 1011, 6 = 1010, 7 = 1001, 8 = 1000, 9 = 1111.
2. Construct 10-state transition table mapping Qn → Qn+1 for 4 T flip-flops (D,C,B,A). Unused 6 combinations set to Don’t Care X.
3. Derive drive equations TD, TC, TB, TA via 4-variable K-maps.

5. Design Example 3: Excess-3 Code Counter [PYQ: 2019, 2022, 2024, 2025]

PYQ Master Problem (2022, 2025): Excess-3 Code Counter

Question: Design a synchronous BCD counter that counts in Excess-3 code (0011_2 → 1100_2) using minimum JK flip-flops. [10 Marks]

Solution Summary:

1. Excess-3 Range: Decimal 0 (0011) → 1 (0100) → 2 (0101) … → 9 (1100) → 0 (0011).
2. States 0000, 0001, 0010, 1101, 1110, 1111 are invalid (Don’t Cares).
3. Map transitions to JK excitation table (0 → 0 = 0X, 0 → 1 = 1X, 1 → 0 = X1, 1 → 1 = X0).
4. K-map optimizations yield drive inputs JD, KD, JC, KC, JB, KB, JA, KA.

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6.04 Specialized Counters (Up-Down, Johnson, Ring & Mod-N ICs)

Beyond standard binary counters, practical digital systems employ specialized counter topologies: Up-Down Counters for reversible position tracking, Ring & Johnson Counters for multi-phase timing signal generation, and Parallel-Load IC Counters (such as the 74161/74163) for modular MOD-N frequency division.

1. Synchronous Binary Up-Down Counter [PYQ: 2018, 2021, 2022, 2023, 2025]

A 4-bit synchronous up-down counter counts upward (0 → 15) when an external control signal Up/Down = 1, and downward (15 → 0) when Up/Down = 0.

1.1 Steering Logic Equations

Using T flip-flops (A3 A2 A1 A0 where A0 is LSB):

• T0 = 1 (LSB toggles on every clock edge).
• T1 = Up · A0 + Up · A0
• T2 = Up · A0 A1 + Up · A0 A1
• T3 = Up · A0 A1 A2 + Up · A0 A1 A2

 Up Line ----⇒[ AND 1 ]----\

[ OR ]---⇒ T1 Drive Logic

Down Line —⇒[ AND 2 ]----/



2. Ring Counter vs. Johnson Counter [PYQ: 2015, 2018, 2019, 2025]

Both Ring and Johnson counters are constructed from shift registers with feedback from the last stage to the first stage.

2.1 Ring Counter (Direct Feedback)

• Architecture: N-bit shift register with the serial output QN-1 connected directly back to the serial input D0.
• Initial State: Preset with a single 1 bit (e.g. 1000).
• Number of Unique States / Timing Signals: Exactly N states for N flip-flops.
• 4-Bit Sequence: 1000 → 0100 → 0010 → 0001 → 1000.

2.2 Johnson Counter (Twisted-Ring / Switch-Tail Counter) [PYQ: 2015, 2018, 2019, 2025]

• Architecture: N-bit shift register with the inverted output QN-1 connected back to serial input D0.
• Initial State: Cleared to all zeros (0000).
• Number of Unique States / Timing Signals: Exactly 2N states for N flip-flops.

4-Bit Johnson Counter State Sequence (N=4 ⇒ 8 States)

Clock Pulse	Q3	Q2	Q1	Q0	Decoded Timing Signal Expression
0	0	0	0	0	T0 = Q3 · Q0
1	1	0	0	0	T1 = Q3 · Q2
2	1	1	0	0	T2 = Q2 · Q1
3	1	1	1	0	T3 = Q1 · Q0
4	1	1	1	1	T4 = Q3 · Q0
5	0	1	1	1	T5 = Q3 · Q2
6	0	0	1	1	T6 = Q2 · Q1
7	0	0	0	1	T7 = Q1 · Q0

Advantage of Johnson Counter over Ring Counter: A Johnson counter generates 2N distinct timing signals using only N flip-flops and 2-input AND decoding gates, whereas a Ring counter requires 2N flip-flops to generate 2N timing signals.

2.3 Comprehensive Counter Comparison Table

Feature	Standard Binary Counter	Ring Counter	Johnson (Twisted-Ring) Counter
Number of Flip-Flops (N)	⌈ log2 M ⌉	M	M / 2
Number of States (M)	2^N	N	2N
Decoding Logic Complexity	High (N-input AND gates required per state).	None (Outputs Qi are directly timing signals).	Low (2-input AND gates required per state).
Self-Starting Ability	Self-starting.	Requires initial preset (1000).	Self-starting / easily initialized (0000).

3. MOD-N Counter Design Using Parallel-Load ICs [PYQ: 2017, 2021]

Integrated Circuit counters (such as the 74161 4-bit binary counter) feature synchronous parallel load inputs (D3 D2 D1 D0), a load enable line (LOAD), and a ripple carry output (RCO).

3.1 Design Methodology for MOD-N Counter using 74161 IC

To design a MOD-6 counter (0 → 5) using a 74161 IC:

1. Method 1 (NAND Clear Feedback): Decode terminal state 510 = 01012 (Q2 · Q0) using a NAND gate connected to active-LOW CLEAR.
2. Method 2 (Parallel Load Preset): Preset parallel inputs to 00002. Connect LOAD to a NAND gate that decodes state 510 = 01012. When state 5 is reached, LOAD = 0, forcing the counter back to 0000 on the next clock pulse.

4. Past Year Master Questions & Solutions

PYQ Master Problem (2015, 2018, 2025): Johnson Counter Design

Question: Construct a Johnson Counter with 10 timing signals. Show the circuit diagram, state table, and decoding logic for all 10 signals. [10 Marks]

Solution:

1. Flip-Flop Count: Number of timing signals = 2N = 10 ⇒ N = 5 flip-flops (E, D, C, B, A).
2. State Table: List 10 states from 00000 → 10000 → 11000 → 11100 → 11110 → 11111 → 01111 → 00111 → 00011 → 00001.
3. Decoding Gates: Show 2-input AND gates decoding adjacent bits (e.g. T0 = E·A, T1 = E·D, …, T9 = B·A).

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6.05 Chapter 6 Master PYQ Solutions & Counter Puzzles

Dedicated problem-solving supplement for Chapter 6 (Registers & Counters). Contains step-by-step worked solutions for the 12-bit register decoding puzzle and complete K-maps/schematics for 4-bit irregular sequence counters asked in past university exams.

1. 12-Bit Register Content Decoding Master Puzzle [PYQ: 2022]

PYQ Master Problem (2022): 12-Bit Register Decoding

Question: The state of a 12-bit register is 100010010111. What is its content if it represents [12 Marks]:

(i) Three decimal digits in BCD?

(ii) Three decimal digits in the Excess-3 code?

(iii) Three decimal digits in the 8, 4, -2, -1 code?

(iv) A binary number?

1.1 Step-by-Step Solution

Divide the 12-bit string into three 4-bit nibbles: 1000, 1001, 0111.

(i) As Three Decimal Digits in BCD (8421 Code)

Evaluate each 4-bit nibble directly into decimal:

• Nibble 1: 1000 = 8

• Nibble 2: 1001 = 9

• Nibble 3: 0111 = 7

Result: 897

(ii) As Three Decimal Digits in Excess-3 Code

Excess-3 is obtained by adding 3 (0011) to each decimal digit. To decode, subtract 3 from each nibble:

• Nibble 1: 1000 (8) - 3 = 5

• Nibble 2: 1001 (9) - 3 = 6

• Nibble 3: 0111 (7) - 3 = 4

Result: 564

(iii) As Three Decimal Digits in 8, 4, -2, -1 Code

Apply weights 8 x B3 + 4 x B2 - 2 x B1 - 1 x B0:

• Nibble 1: 1000 → 8(1) + 4(0) - 2(0) - 1(0) = 8

• Nibble 2: 1001 → 8(1) + 4(0) - 2(0) - 1(1) = 8 - 1 = 7

• Nibble 3: 0111 → 8(0) + 4(1) - 2(1) - 1(1) = 4 - 2 - 1 = 1

Result: 871

(iv) As a Pure Binary Number

Evaluate the 12-bit string 100010010111 as a single base-2 integer:

100010010111 = 2048 + 128 + 16 + 4 + 2 + 1 = 2199

2. Irregular Sequence Counter 1: 15 → 10 → 9 → 8 → 7 → 6 [PYQ: 2015, 2020]

PYQ Master Problem (2015, 2020): Sequence Counter Design

Question: Design a synchronous counter that will count 15 → 10 → 9 → 8 → 7 → 6 and repeat using JK flip-flops [13 Marks].

2.1 State & Excitation Table

Flip-flops D, C, B, A (where D is MSB). Unused states (0-5, 11-14) are Don’t Cares (X).

Present State	Next State	JD, KD	JC, KC	JB, KB	JA, KA
0110 (6)	1111 (15)	1 X	X 0	X 0	1 X
0111 (7)	0110 (6)	0 X	X 0	X 0	X 1
1000 (8)	0111 (7)	X 1	1 X	1 X	1 X
1001 (9)	1000 (8)	X 0	0 X	0 X	X 1
1010 (10)	1001 (9)	X 0	0 X	X 0	1 X
1111 (15)	1010 (10)	X 0	X 1	X 0	X 1

2.2 K-Map Drive Equations

• JD = A’, KD = C

• JC = A’, KC = A

• JB = D’, KB = 0

• JA = C’ + B’, KA = 1

3. Irregular Sequence Counter 2: 15 → 11 → 9 → 8 → 4 → 6 → 1 [PYQ: 2024]

PYQ Master Problem (2024): 7-State T Flip-Flop Counter

Question: Design a counter that will follow the sequence 15 → 11 → 9 → 8 → 4 → 6 → 1 and repeat using T flip-flops [12 Marks].

3.1 State & Excitation Table (T FF Excitation: T = Qn ⊕ Qn+1)

Present State	Next State	TD	TC	TB	TA
0001 (1)	1111 (15)	1	1	1	0
0100 (4)	0110 (6)	0	0	1	0
0110 (6)	0001 (1)	0	1	1	1
1000 (8)	0100 (4)	1	1	0	0
1001 (9)	1000 (8)	0	0	0	1
1011 (11)	1001 (9)	0	0	1	0
1111 (15)	1011 (11)	0	1	1	0

3.2 Drive Logic Equations

• TD = D’ C’ A + D C’ B’ A’

• TC = D’ C’ A + D B’ A’ + C B A’ + C B A

• TB = D’ C’ A + D C B A + D C’ B A + D’ C A’

• TA = D C’ B’ A + D’ C B A’

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6.06 Register Architectures, Parallel Load & Shift Register Topologies

aliases:

• Registers vs Counters Matrix
• 4-Bit Parallel Load Register Schematic
• Shift Register Topologies (SISO, SIPO, PISO, PIPO)
• Shift Register Content Tracker
• 12-Bit Register Content Decoding

tags:

• digital-electronics
• ece-2103
• term-2-1
• study-order/6.06

type: uni-note

course: “ECE 2103 - Digital Electronics and Logic Circuits”

chapter_map: “06 Chapter Map - Registers & Counters”

term: 2-1

teacher: Foysal Sir

status: enhanced

Related Concepts: 6.01 Registers, Parallel Load & Shift Register Dynamics | 6.02 Asynchronous (Ripple) Counters & Propagation Delay Calculations | 6.05 Chapter 6 Master PYQ Solutions & Counter Puzzles

6.06 Register Architectures, Parallel Load & Shift Register Topologies

Overview Registers store and manipulate multi-bit binary data. Understanding parallel load steering logic, shift register topologies (SISO, SIPO, PISO, PIPO), serial tracking numericals, and multi-code register decoding is essential for digital system design.

1. Registers vs. Counters Comparison Matrix

Feature	Register	Counter
Primary Function	Storing and transferring multi-bit data words.	Tracking and counting pulse sequences / events.
State Sequence	Arbitrary (depends on external data input).	Deterministic cyclic sequence ($0,1,2,\dots ,N$).
Clocking	All flip-flops clocked simultaneously.	Can be Asynchronous (Ripple) or Synchronous.
Primary Building Block	Parallel-load or Shift Registers.	Synchronous / Asynchronous Counters.

2. 4-Bit Parallel Load Register Architecture [PYQ: 2015, 2016, 2017, 2021, 2023, 2025]

To prevent stored data from being overwritten on every clock edge, a Parallel Load Line ($Load$) controls 2-to-1 MUXes at each D flip-flop input.

 Load Line

|

v

I_i -⇒[ 1 ]

[ MUX ]---⇒ D_i -⇒[ D FLIP-FLOP ]---⇒ A_i (Output)

A_i -⇒[ 0 ] |

CLK

2.1 Boolean Input Equation

$D\_i=Load\cdot I\_i+\overline{Load}\cdot A\_i$

3. Shift Register Topologies & Use-Cases

1. SISO (Serial-In, Serial-Out): Used for time-delay generation and long-distance serial data links.
2. SIPO (Serial-In, Parallel-Out): Converts serial data streams into parallel words (e.g., UART receivers).
3. PISO (Parallel-In, Serial-Out): Converts parallel bus words into serial bitstreams (e.g., UART transmitters).
4. PIPO (Parallel-In, Parallel-Out): Temporary internal CPU registers (e.g., Accumulator, Instruction Register).

4. Shift Register Content Tracker Tutorial [PYQ: 2017–2025]

4.1 4-Bit Right Shift Example

• Initial Content: $A\_3A\_2A\_1A\_0=1101$.
• Serial Input Stream: 101101 (applied LSB first).

Pulse	Serial In	$A\_3$	$A\_2$	$A\_1$	$A\_0$	Serial Output
0	—	1	1	0	1	—
1	1	1	1	1	0	1
2	0	0	1	1	1	0
3	1	1	0	1	1	1
4	1	1	1	0	1	1

5. 12-Bit Register Multi-Code Decoding Puzzle [PYQ: 2022]

Register State: 100010010111 (Nibbles: 1000, 1001, 0111).

• BCD Code: 1000=8, 1001=9, 0111=7 $⟹$ 897.
• Excess-3 Code: Subtract 3: 8-3=5, 9-3=6, 7-3=4 $⟹$ 564.
• 8, 4, -2, -1 Code: $8(1)+4(0)-2(0)-1(0)=8$, $8(1)-1(1)=7$, $4(1)-2(1)-1(1)=1⟹$ 871.
• Binary Integer: $100010010111\_2=2199\_10$.

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6.07 Ripple Counters, Delay Timing Equations & Truncated Moduli

Overview: Asynchronous (ripple) counters simplify clock routing because only the LSB flip-flop is clocked externally. However, cumulative propagation delays limit the maximum operating frequency f_max.

Related Concepts: 6.02 Asynchronous (Ripple) Counters & Propagation Delay Calculations | 6.03 Synchronous Counter Design (Sequence, Code & BCD Counters) | 6.08 Synchronous Counter Synthesis, Lock-Out & Specialized Counters

1. Asynchronous (Ripple) vs. Synchronous Counters

Feature	Ripple Counter	Synchronous Counter
Clock Line	Only 1st FF receives external clock.	All FFs clocked simultaneously.
Total Propagation Delay	t_total = N x t_pd	t_total = t_pd + t_gate
Maximum Operating Speed	Low (f_max = 1 / (N * t_pd)).	High (f_max = 1 / (t_pd + t_gate)).
Decoding Glitches	Present due to intermediate rippling states.	Absent (all state changes settle together).

2. Delay Timing Equations & Numerical Proof [PYQ: 2018]

For an N-bit ripple counter where each flip-flop has propagation delay t_pd:

t_total = N x t_pd ⇒ f_max = 1 / (N x t_pd)

Problem (10-Bit Counter with t_pd = 20 ns):

* Total Delay: t_total = 10 x 20 ns = 200 ns.

* Max Frequency: f_max = 1 / (200 x 10^-9 s) = 5 MHz.

3. Truncated Decade Ripple Counter (MOD-10)

To reset at count 10_10 = 1010_2 (Q3 Q2 Q1 Q0 = 1010):

/CLR = /(Q3 . Q1)

Connecting a NAND gate decoding Q3 and Q1 to all active-LOW /CLR pins resets the counter asynchronously back to 0000.

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6.08 Synchronous Counter Synthesis, Lock-Out & Specialized Counters

Advanced counter design encompasses self-starting state recovery (eliminating lock-out), Ring/Johnson timing generators, reversible up-down counting, and modular MOD-N IC implementation.

1. Unused States & Self-Starting Counter Design

Definition: The Lock-Out Problem

If noise forces a counter into an unused state, and the next-state logic transitions only among unused states, the counter enters an infinite loop called Lock-Out.

Self-Starting Requirement: Designing drive logic so that every unused state transitions back into a valid count state within 1 or 2 clock pulses.

2. Johnson Counter vs. Ring Counter

 Ring Counter (Direct Feedback Q_N-1 → D_0): N Flip-Flops -⇒ N Timing Signals

Johnson Counter (Inverted Feedback Q’_N-1 → D_0): N Flip-Flops -⇒ 2N Timing Signals

2.1 5-Flip-Flop Johnson Counter (10 Timing Signals) [PYQ: 2015, 2018, 2019, 2025]

• Sequence (E D C B A): 00000 → 10000 → 11000 → 11100 → 11110 → 11111 → 01111 → 00111 → 00011 → 00001 → 00000.
• Decoded Signals: T_0 = E’A’, T_1 = ED’, …, T_9 = B’A.

3. 4-Bit Synchronous Up-Down Counter [PYQ: 2018, 2021, 2022, 2023, 2025]

With control signal M (M=0 for Up, M=1 for Down):

• T_0 = 1
• T_1 = M’ A_0 + M A_0’
• T_2 = M’ A_0 A_1 + M A_0’ A_1’
• T_3 = M’ A_0 A_1 A_2 + M A_0’ A_1’ A_2’

4. Mod-6 Counter Wiring Schematic using 74163 IC [PYQ: 2017, 2021]

The 74163 is a 4-bit synchronous binary counter with active-LOW parallel load (LOAD’).

• Method: Preset D_3 D_2 D_1 D_0 = 0000. Connect a NAND gate decoding count 5_10 = 0101_2 (Q_2 * Q_0) to LOAD’. When count reaches 5, LOAD’ = 0, resetting counter to 0000 on the next clock pulse.

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00 Chapter 6 Active-Recall Diagnostic Quiz (Registers & Counters)

Test your conceptual understanding and exam readiness for registers, shift registers, ripple counters, synchronous counters, and specialized counters.

Question 1: Parallel Load Register Operation

In a 4-bit register with parallel load control (Load), what is the Boolean input equation Di for each D flip-flop stage?

Solution:

Di = Load · Ii + Load’ · Ai

When Load=1, Di = Ii (new data loaded). When Load=0, Di = Ai (present output held).

Question 2: Serial vs. Parallel Data Transfer Trade-off

Compare Serial Transfer vs. Parallel Transfer in terms of hardware wire count and clock cycles required.

Solution:

• Serial Transfer: Requires 1 transmission line and N clock cycles to transfer an N-bit word (slow, low hardware cost).
• Parallel Transfer: Requires N transmission lines and 1 clock cycle to transfer an N-bit word (fast, high hardware cost).

Question 3: Ripple Counter Clock Propagation

Why is an asynchronous counter called a “ripple” counter?

Solution:

Only the LSB flip-flop receives the external system clock. Each subsequent flip-flop is clocked by the output transition of the preceding flip-flop, causing state changes to ripple sequentially down the cascade like a wave.

Question 4: Maximum Frequency Formula for Ripple Counters

Write the formula for the maximum operating clock frequency f_max of an N-bit ripple counter with propagation delay t_pd per flip-flop.

Solution:

f_max = 1 / t_total = 1 / (N · t_pd)

Question 5: Truncated Decade Counter Reset Logic

In a 4-bit binary ripple counter (Q3 Q2 Q1 Q0), what NAND gate logic must be connected to the active-LOW CLR’ pins to construct a Decade (MOD-10) counter?

Solution:

Decode state 10_10 = 1010_2 (Q3=1, Q1=1):

CLR’ = (Q3 · Q1)’

Momentary entry into state 1010 causes CLR’ = 0, resetting all flip-flops immediately to 0000.

Question 6: Asynchronous vs. Synchronous Delay Advantage

Why do synchronous counters operate at much higher maximum clock frequencies than ripple counters for large N?

Solution:

In a synchronous counter, all flip-flops are clocked simultaneously by the master clock, making total delay fixed (t_total = t_pd + t_gate) regardless of bit count N. In a ripple counter, delay grows linearly with N (t_total = N · t_pd).

Question 7: Ring Counter vs. Johnson Counter State Efficiency

For an N-bit shift register, how many unique timing signals are generated by a Ring Counter vs. a Johnson Counter?

Solution:

• Ring Counter (N flip-flops): Generates N unique states/timing signals (direct feedback Q_{N-1} → D0).
• Johnson Counter (N flip-flops): Generates 2N unique states/timing signals (inverted feedback Q_{N-1}’ → D0).

Question 8: Johnson Counter 4-Bit Sequence

List the 8-state binary sequence of a 4-bit Johnson counter starting from 0000.

Solution:

0000 → 1000 → 1100 → 1110 → 1111 → 0111 → 0011 → 0001 → 0000

Question 9: 12-Bit Register Decoding

A 12-bit register holds 100010010111. What decimal values does this represent in BCD and Excess-3?

Solution:

• BCD: 1000 = 8, 1001 = 9, 0111 = 7 ⇒ 897.
• Excess-3: Subtract 3 from each nibble: 1000-3 = 5, 1001-3 = 6, 0111-3 = 4 ⇒ 564.

Question 10: Shift Register Tracking

A 4-bit register initially contains 1011. What is the content after 2 right shifts if the serial input stream is 10 (applied LSB first: bit 0 then bit 1)?

Solution:

• Initial: 1011
• Shift 1 (input 0): 0101
• Shift 2 (input 1): 1010
• Result after 2 shifts: 1010