Related Concepts: 6.01 Registers, Parallel Load & Shift Register Dynamics | 6.02 Asynchronous (Ripple) Counters & Propagation Delay Calculations | 6.04 Specialized Counters (Up-Down, Johnson, Ring & Mod-N ICs)

6.03 Synchronous Counter Design (Sequence, Code & BCD Counters)

Counter design appears in every single paper

Three question families, 10–15 marks each, all using the identical five-step procedure in §2:

Family	Appearances	Section
Irregular sequence (15-10-9-…)	7	§3
Excess-3 code counter	4	§5
84-2-1 code counter	3	§4

All three are fully derived and verified below.

In a Synchronous Counter, the clock input is connected directly to the clock terminals of all flip-flops simultaneously. This eliminates cumulative propagation delay, allowing synchronous counters to operate at much higher clock frequencies than ripple counters.

1. Asynchronous vs. Synchronous Counter Comparison

Feature	Asynchronous (Ripple) Counter	Synchronous Counter
Clock Signal Connection	Only 1st FF is clocked externally; subsequent FFs clocked by preceding FF outputs.	All FFs clocked simultaneously by the master system clock.
Propagation Delay	Cumulative (t_total = N x t_pd). Grows linearly with bit count N.	Fixed (t_total = t_pd + t_gate). Independent of bit count N.
Maximum Frequency	Low (f_max = 1 / (N * t_pd)).	High (f_max = 1 / (t_pd + t_gate)).
Glitch Susceptibility	High (transient decoding errors occur during rippling).	Low (state transitions settle simultaneously).
Design Flexibility	Limited to straight binary or simple truncated counters.	Unlimited. Can count any arbitrary sequence or non-weighted code.

2. Systematic Synchronous Counter Synthesis Procedure

1. Step 1: Determine Required Number of Flip-Flops N = ceil(log2 M)
2. Step 2: Construct Combined State & Excitation Table
3. Step 3: Minimize Flip-Flop Input Logic using K-Maps
4. Step 4: Draw Final Synchronous Circuit Schematic

3. Design Example 1: Irregular Sequence Counter

Seven appearances — the most repeated design question in Chapter 6

Only the digit order changes between years:

Sequence	Flip-flop	Years	Marks
15-10-9-8-7-6	JK	2015 (13), 2020 (10)	10–13
15-10-9-7-8-6	JK	2016 (15), 2022 (13)	13–15
15-10-9-7-8-6	T	2023	13
15-10-9-8-6-7	T	2025	13
15-11-9-8-4-6-1	T	2024	12

Every version starts at 15 and uses 4 flip-flops with 10 unused states as don’t cares. Learn the procedure on the worked example below and you can execute any variant.

Worked Exam Problem (PYQ 2015 — 13 marks; 2020 — 10 marks)

Question (verbatim): Design a synchronous counter that will count 15-10-9-8-7-6 and repeat by using JK flip-flops.

Step 1 — Flip-Flop Count and Don’t Cares

Highest value is $15=1111_2$, so 4 JK flip-flops are needed: $Q_D{Q}_C{Q}_B{Q}_A$ (MSB to LSB).

Only six of the sixteen states are used. The other ten — 0, 1, 2, 3, 4, 5, 11, 12, 13, 14 — never occur and become don’t cares in every K-map. This is what makes the final equations so short.

Step 2 — State Transition and JK Excitation Table

Recall the JK excitation rules: $0\to 0$ gives $J=0,K=\times$; $0\to 1$ gives $J=1,K=\times$; $1\to 0$ gives $J=\times ,K=1$; $1\to 1$ gives $J=\times ,K=0$.

Present	$Q_D{Q}_C{Q}_B{Q}_A$	Next	$Q_D^{+}{Q}_C^{+}{Q}_B^{+}{Q}_A^{+}$	$J_D{K}_D$	$J_C{K}_C$	$J_B{K}_B$	$J_A{K}_A$
15	1111	10	1010	$\times 0$	$\times 1$	$\times 0$	$\times 1$
10	1010	9	1001	$\times 0$	$0\times$	$\times 1$	$1\times$
9	1001	8	1000	$\times 0$	$0\times$	$0\times$	$\times 1$
8	1000	7	0111	$\times 1$	$1\times$	$1\times$	$1\times$
7	0111	6	0110	$0\times$	$\times 0$	$\times 0$	$\times 1$
6	0110	15	1111	$1\times$	$\times 0$	$\times 0$	$1\times$

Step 3 — K-Map Minimisation

With ten don’t-care cells the maps collapse almost immediately:

$J_D=Q_A^{\prime }{K}_D=Q_B^{\prime }{Q}_A^{\prime }$ $J_C=Q_B^{\prime }{Q}_A^{\prime }{K}_C=Q_D$ $J_B=Q_A^{\prime }{K}_B=Q_C^{\prime }{Q}_A^{\prime }$ ${\mathbf{J}}_{\mathbf{A}}={\mathbf{K}}_{\mathbf{A}}=1$

Reading $J_A=K_A=1$: the LSB toggles on every clock. Confirm it against the sequence — 15, 10, 9, 8, 7, 6 alternates odd, even, odd, even, odd, even. It does.

Step 4 — Verification

Substituting each present state back into the equations must reproduce the next state. Checking state 8 (1000):

• $J_D=Q_A^{\prime }=1$, $K_D=Q_B^{\prime }{Q}_A^{\prime }=1⟹Q_D$ toggles $1\to 0$ ✓
• $J_C=Q_B^{\prime }{Q}_A^{\prime }=1$, $K_C=Q_D=1⟹Q_C$ toggles $0\to 1$ ✓
• $J_B=Q_A^{\prime }=1$, $K_B=Q_C^{\prime }{Q}_A^{\prime }=1⟹Q_B$ toggles $0\to 1$ ✓
• $J_A=K_A=1⟹Q_A$ toggles $0\to 1$ ✓

Result 0111 = 7 ✓. All six transitions check out. $■$

Step 5 — Circuit

Four JK flip-flops sharing one clock, with the input logic above: $Q_A$‘s $J$ and $K$ tied HIGH, and small AND/NOT networks generating the other six inputs.

Exam technique for any sequence-counter variant

1. Always verify by substitution — it takes a minute and catches every K-map slip. Show at least one verified transition; examiners give credit for it.
2. Use the unused states as don’t cares. Forgetting this yields correct but bloated equations and loses simplification marks.
3. For T flip-flops (2023, 2024, 2025 versions) the table is simpler: $T=Q_n\oplus Q_n^{+}$, so one column per flip-flop instead of two. Same procedure otherwise.
4. Mention lock-out. Because ten states are unused, the counter could power up in one of them and never reach the sequence. Noting that a self-correcting design or a reset is required shows design awareness — see 6.04 Specialized Counters (Up-Down, Johnson, Ring & Mod-N ICs).

4. Design Example 2: Code Counter in 84-2-1 Code

Exam Problem (PYQ 2016 — 12 marks; 2017 — 11 marks; 2020 — 10 marks)

Question (verbatim): Design a counter that counts the decimal digits according to $84\bar{2}\bar{1}$ code using T flip-flop.

Step 1 — The Sequence

The 84-2-1 code (weights $8,4,-2,-1$) runs:

Decimal	0	1	2	3	4	5	6	7	8	9
Code	0000	0111	0110	0101	0100	1011	1010	1001	1000	1111

Four T flip-flops $Q_3{Q}_2{Q}_1{Q}_0$. Unused states 0001, 0010, 0011, 1100, 1101, 1110 are don’t cares.

Step 2 — Transition and T Excitation Table

Recall $T=Q_n\oplus Q_n^{+}$ — the flip-flop toggles exactly when the bit changes.

Dec	Present	Next	$T_3$	$T_2$	$T_1$	$T_0$
0	0000	0111	0	1	1	1
1	0111	0110	0	0	0	1
2	0110	0101	0	0	1	1
3	0101	0100	0	0	0	1
4	0100	1011	1	1	1	1
5	1011	1010	0	0	0	1
6	1010	1001	0	0	1	1
7	1001	1000	0	0	0	1
8	1000	1111	0	1	1	1
9	1111	0000	1	1	1	1

Step 3 — Minimised Drive Equations

${\mathbf{T}}_0=1$ ${\mathbf{T}}_1={\mathbf{Q}}_0^{\prime }+{\mathbf{Q}}_3{\mathbf{Q}}_2$ ${\mathbf{T}}_2={\mathbf{Q}}_1^{\prime }{\mathbf{Q}}_0^{\prime }+{\mathbf{Q}}_3{\mathbf{Q}}_2$ ${\mathbf{T}}_3={\mathbf{Q}}_2\left({\mathbf{Q}}_3+{\mathbf{Q}}_1^{\prime }{\mathbf{Q}}_0^{\prime }\right)$

The $T_0=1$ column is a free sanity check: the code’s LSB alternates on every step of the sequence, and it does.

Step 4 — Verification

State 0100 (decimal 4) $\to$ 1011:

• $T_3=Q_2(Q_3+Q_1^{\prime }{Q}_0^{\prime })=1(0+1\cdot 1)=1⟹Q_3$ toggles $0\to 1$ ✓
• $T_2=Q_1^{\prime }{Q}_0^{\prime }+Q_3{Q}_2=1+0=1⟹Q_2$ toggles $1\to 0$ ✓
• $T_1=Q_0^{\prime }+Q_3{Q}_2=1+0=1⟹Q_1$ toggles $0\to 1$ ✓
• $T_0=1⟹Q_0$ toggles $0\to 1$ ✓ $⟹$ 1011 ✓

State 1111 (decimal 9) $\to$ 0000:

• $T_3=1(1+0)=1$, $T_2=0+1=1$, $T_1=0+1=1$, $T_0=1$ — all four toggle $⟹$ 0000 ✓ $■$

The trap in this question

84-2-1 is not a counting sequence in binary order. Going from decimal 4 (0100) to decimal 5 (1011) flips every bit. If you write the states as plain binary 0–9 instead of looking up the 84-2-1 code, the entire design is wrong from step 1.

Write out the code table first, exactly as in Step 1, and label each row with its decimal value. That table alone is worth marks — see 2.01 BCD & Weighted Digital Codes for how to verify each row by weight-sum ($8Q_3+4Q_2-2Q_1-Q_0$).

5. Design Example 3: Excess-3 Code Counter

Exam Problem (PYQ 2019, 2022 — 13 marks with T flip-flops; 2024 — 13 marks, 2025 — 10 marks with JK)

Question (verbatim, 2022): Design a counter that counts the decimal digits according to Excess-3 code using T flip-flop. Question (verbatim, 2024/2025): Design a decade counter to count excess-3 code sequence using minimum number of J-K flip-flops.

Note the flip-flop type changes by year: T in 2019 and 2022, JK in 2024 and 2025. The state sequence is identical — Excess-3 runs 0011 (decimal 0) through 1100 (decimal 9), so states 0000–0010 and 1101–1111 are the six don’t cares.

Step 1 — The Sequence

Excess-3 encodes decimal $d$ as binary $(d+3)$, so the counter simply counts binary 3 up to 12, then wraps back to 3:

$0011\to 0100\to 0101\to 0110\to 0111\to 1000\to 1001\to 1010\to 1011\to 1100\to 0011$

Four JK flip-flops $Q_3{Q}_2{Q}_1{Q}_0$. Unused states 0000, 0001, 0010, 1101, 1110, 1111 are don’t cares.

Step 2 — State Transition and JK Excitation Table

Dec	Present	Next	$J_3{K}_3$	$J_2{K}_2$	$J_1{K}_1$	$J_0{K}_0$
0	0011	0100	$0\times$	$1\times$	$\times 1$	$\times 1$
1	0100	0101	$0\times$	$\times 0$	$0\times$	$1\times$
2	0101	0110	$0\times$	$\times 0$	$1\times$	$\times 1$
3	0110	0111	$0\times$	$\times 0$	$\times 0$	$1\times$
4	0111	1000	$1\times$	$\times 1$	$\times 1$	$\times 1$
5	1000	1001	$\times 0$	$0\times$	$0\times$	$1\times$
6	1001	1010	$\times 0$	$0\times$	$1\times$	$\times 1$
7	1010	1011	$\times 0$	$0\times$	$\times 0$	$1\times$
8	1011	1100	$\times 0$	$1\times$	$\times 1$	$\times 1$
9	1100	0011	$\times 1$	$\times 1$	$1\times$	$1\times$

Step 3 — Minimised Drive Equations

${\mathbf{J}}_0={\mathbf{K}}_0=1$ ${\mathbf{J}}_1={\mathbf{Q}}_0+{\mathbf{Q}}_3{\mathbf{Q}}_2{\mathbf{K}}_1={\mathbf{Q}}_0$ ${\mathbf{J}}_2={\mathbf{Q}}_1{\mathbf{Q}}_0{\mathbf{K}}_2={\mathbf{Q}}_1{\mathbf{Q}}_0+{\mathbf{Q}}_3$ ${\mathbf{J}}_3={\mathbf{Q}}_2{\mathbf{Q}}_1{\mathbf{Q}}_0{\mathbf{K}}_3={\mathbf{Q}}_2$

Step 4 — Verification

The two transitions worth checking are the wrap-around and the carry across the nibble.

State 1100 (decimal 9) $\to$ 0011:

• $J_3=Q_2{Q}_1{Q}_0=0$, $K_3=Q_2=1⟹Q_3$ toggles $1\to 0$ ✓
• $J_2=Q_1{Q}_0=0$, $K_2=Q_1{Q}_0+Q_3=0+1=1⟹Q_2$ toggles $1\to 0$ ✓
• $J_1=Q_0+Q_3{Q}_2=0+1=1$, $K_1=Q_0=0⟹Q_1:0\to 1$ ✓
• $J_0=K_0=1⟹Q_0$ toggles $0\to 1$ ✓ $⟹$ 0011 ✓

State 0111 (decimal 4) $\to$ 1000:

• $J_3=Q_2{Q}_1{Q}_0=1⟹Q_3:0\to 1$ ✓
• $J_2=1,K_2=1⟹Q_2$ toggles $1\to 0$ ✓
• $J_1=1,K_1=1⟹Q_1$ toggles $1\to 0$ ✓
• $Q_0$ toggles $1\to 0$ ✓ $⟹$ 1000 ✓ $■$

The shortcut worth spotting

Excess-3 is just binary counting shifted by 3, so the drive equations look almost exactly like an ordinary binary up-counter ($J_0=K_0=1$, each higher bit toggling on the AND of all lower bits). The only differences are the extra $Q_3{Q}_2$ term in $J_1$ and the $Q_3$ term in $K_2$, which together force the wrap from 12 back to 3 instead of to 0. Saying this explicitly demonstrates understanding rather than mechanical table-filling.

For the T flip-flop versions (2019, 2022) use $T=Q_n\oplus Q_n^{+}$ — one column per flip-flop instead of two, and the same don’t cares.

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6. Past Year Questions (PYQs)

PYQ Index for this note

Question (as asked)	Years	Marks	Solved in
Design a synchronous counter that will count 15-10-9-8-7-6 and repeat using JK flip-flops	2015 (13), 2020 (10)	10–13	§3
Design a synchronous counter that will count 15-10-9-7-8-6 and repeat using JK flip-flops	2016 (15), 2022 (13)	13–15	§3 method
Design a synchronous counter that will count 15-10-9-7-8-6 and repeat using T flip-flop	2023	13	§3 method
Design a synchronous counter that will count 15-10-9-8-6-7 and repeat using T flip-flop	2025	13	§3 method
Design a counter following 15-11-9-8-4-6-1 and repeat using T flip-flop	2024	12	§3 method
Design a counter that counts decimal digits according to 84-2-1 code using T flip-flop	2016 (12), 2017 (11), 2020 (10)	10–12	§4
Design a counter that counts decimal digits according to Excess-3 code using T flip-flop	2019, 2022	13	§5
Design a decade counter for the Excess-3 sequence using minimum J-K flip-flops	2024 (13), 2025 (10)	10–13	§5
Design a BCD counter with JK flip-flops	2019	10	§5 method

Pattern to notice: counter design appears in every single paper, worth 10–15 marks, and it is always one of three families — irregular sequence (7 appearances), 84-2-1 code (3), or Excess-3 (4). The procedure never changes:

flip-flop count → state/excitation table → K-maps with unused states as don’t cares → verify by substitution → draw.

The variable to check each year is the flip-flop type — JK in 2015, 2016, 2019, 2020, 2022, 2024, 2025; T in 2016, 2017, 2020, 2023, 2025. Using the wrong excitation table produces a completely wrong answer from step 2 onward.

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7. Related Notes

• 6.04 Specialized Counters (Up-Down, Johnson, Ring & Mod-N ICs) — up-down, Johnson, ring and Mod-N designs, plus lock-out
• 6.02 Asynchronous (Ripple) Counters & Propagation Delay Calculations — the ripple alternative and its delay limits
• 5.01 Sequential Logic Fundamentals, Latches & Flip-Flops (SR & JK) — the JK and T excitation tables this whole note depends on