6.07 Ripple Counters, Delay Timing Equations & Truncated Moduli

Overview: Asynchronous (ripple) counters simplify clock routing because only the LSB flip-flop is clocked externally. However, cumulative propagation delays limit the maximum operating frequency f_max.

Related Concepts: 6.02 Asynchronous (Ripple) Counters & Propagation Delay Calculations | 6.03 Synchronous Counter Design (Sequence, Code & BCD Counters) | 6.08 Synchronous Counter Synthesis, Lock-Out & Specialized Counters

1. Asynchronous (Ripple) vs. Synchronous Counters

Feature	Ripple Counter	Synchronous Counter
Clock Line	Only 1st FF receives external clock.	All FFs clocked simultaneously.
Total Propagation Delay	t_total = N x t_pd	t_total = t_pd + t_gate
Maximum Operating Speed	Low (f_max = 1 / (N * t_pd)).	High (f_max = 1 / (t_pd + t_gate)).
Decoding Glitches	Present due to intermediate rippling states.	Absent (all state changes settle together).

2. Delay Timing Equations & Numerical Proof [PYQ: 2018]

For an N-bit ripple counter where each flip-flop has propagation delay t_pd:

t_total = N x t_pd ⇒ f_max = 1 / (N x t_pd)

Problem (10-Bit Counter with t_pd = 20 ns):

* Total Delay: t_total = 10 x 20 ns = 200 ns.

* Max Frequency: f_max = 1 / (200 x 10^-9 s) = 5 MHz.

3. Truncated Decade Ripple Counter (MOD-10)

To reset at count 10_10 = 1010_2 (Q3 Q2 Q1 Q0 = 1010):

/CLR = /(Q3 . Q1)

Connecting a NAND gate decoding Q3 and Q1 to all active-LOW /CLR pins resets the counter asynchronously back to 0000.