6.08 Synchronous Counter Synthesis, Lock-Out & Specialized Counters

Advanced counter design encompasses self-starting state recovery (eliminating lock-out), Ring/Johnson timing generators, reversible up-down counting, and modular MOD-N IC implementation.

1. Unused States & Self-Starting Counter Design

Definition: The Lock-Out Problem

If noise forces a counter into an unused state, and the next-state logic transitions only among unused states, the counter enters an infinite loop called Lock-Out.

Self-Starting Requirement: Designing drive logic so that every unused state transitions back into a valid count state within 1 or 2 clock pulses.

2. Johnson Counter vs. Ring Counter

 Ring Counter (Direct Feedback Q_N-1 → D_0): N Flip-Flops -⇒ N Timing Signals

Johnson Counter (Inverted Feedback Q’_N-1 → D_0): N Flip-Flops -⇒ 2N Timing Signals

2.1 5-Flip-Flop Johnson Counter (10 Timing Signals) [PYQ: 2015, 2018, 2019, 2025]

• Sequence (E D C B A): 00000 → 10000 → 11000 → 11100 → 11110 → 11111 → 01111 → 00111 → 00011 → 00001 → 00000.
• Decoded Signals: T_0 = E’A’, T_1 = ED’, …, T_9 = B’A.

3. 4-Bit Synchronous Up-Down Counter [PYQ: 2018, 2021, 2022, 2023, 2025]

With control signal M (M=0 for Up, M=1 for Down):

• T_0 = 1
• T_1 = M’ A_0 + M A_0’
• T_2 = M’ A_0 A_1 + M A_0’ A_1’
• T_3 = M’ A_0 A_1 A_2 + M A_0’ A_1’ A_2’

4. Mod-6 Counter Wiring Schematic using 74163 IC [PYQ: 2017, 2021]

The 74163 is a 4-bit synchronous binary counter with active-LOW parallel load (LOAD’).

• Method: Preset D_3 D_2 D_1 D_0 = 0000. Connect a NAND gate decoding count 5_10 = 0101_2 (Q_2 * Q_0) to LOAD’. When count reaches 5, LOAD’ = 0, resetting counter to 0000 on the next clock pulse.