Related Concepts: 6.01 Registers, Parallel Load & Shift Register Dynamics | 6.03 Synchronous Counter Design (Sequence, Code & BCD Counters) | 6.04 Specialized Counters (Up-Down, Johnson, Ring & Mod-N ICs)

6.02 Asynchronous (Ripple) Counters & Propagation Delay Calculations

The definition is asked five times; the numerical once

“What is ripple counter?” opens the up-down counter question in 2018, 2022, 2023 and 2025 (see 6.04 Specialized Counters (Up-Down, Johnson, Ring & Mod-N ICs) §1). The delay numerical in §2 appeared once, in 2018, but was worth 13 marks.

Overview: An Asynchronous Counter (commonly known as a Ripple Counter) is a sequential counting circuit where flip-flops are not clocked simultaneously. Instead, only the first flip-flop (LSB) receives the external system clock; each subsequent flip-flop is clocked by the output transition of the preceding flip-flop.

1. 4-Bit Binary Ripple Up-Counter

The definition to have ready

“A ripple (asynchronous) counter is one in which only the first flip-flop is driven by the system clock; each subsequent flip-flop is clocked by the output of the preceding stage, so state changes propagate — ripple — through the chain rather than occurring simultaneously.”

Add the consequence — cumulative propagation delay limiting maximum frequency — and you have the full answer to the “What is ripple counter?” clause that opens the 2018, 2022, 2023 and 2025 up-down counter questions.

A 4-bit binary ripple up-counter counts sequentially from 0000₂ (0₁₀) to 1111₂ (15₁₀) using 4 negative-edge triggered JK flip-flops set to Toggle mode (J = K = 1).

1.1 Circuit Diagram & Connection Rules

 System CLK —⇒(CLK) [ FF 0 ]---⇒ Q0 (LSB)

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(CLK) [ FF 1 ]---⇒ Q1

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(CLK) [ FF 2 ]---⇒ Q2

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(CLK) [ FF 3 ]---⇒ Q3 (MSB)

Connection Rule for Up-Counter vs. Down-Counter: • Up-Counter (Negative-Edge FFs): Connect Qᵢ to CLKᵢ₊₁. • Down-Counter (Negative-Edge FFs): Connect Q̅ᵢ to CLKᵢ₊₁.

2. Propagation Delay & Maximum Operating Frequency

Because transitions ripple sequentially through the cascade of N flip-flops, the total time required for a state update to settle across the entire counter is cumulative.

2.1 Mathematical Formulas

1. Total Cumulative Propagation Delay (t_total): For an N-bit ripple counter where each flip-flop has a propagation delay t_pd: t_total = N × t_pd

2. Maximum Operating Frequency (f_max): To ensure reliable operation without output corruption before settling: f_max = 1 / t_total = 1 / (N × t_pd)

Worked Exam Problem (PYQ 2018 — 13 marks)

Question (verbatim): A flip-flop has a 20-ns delay from the time its CP input goes from 1 to 0 to the time the output is complemented. What is the maximum delay in a 10-bit binary ripple counter that uses these flip-flops? What is the maximum frequency the counter can operate at reliably?

Solution:

1. Given: Number of bits N = 10, Propagation delay per flip-flop t_pd = 20 ns = 20 × 10⁻⁹ s.
2. Total Delay (t_total): t_total = N × t_pd = 10 × (20 ns) = 200 ns
3. Maximum Operating Frequency (f_max): f_max = 1 / t_total = 1 / (200 × 10⁻⁹ s) = 5 × 10⁶ Hz = 5 MHz

Why the worst case is all 10 stages

The delay is only cumulative when every flip-flop must toggle — which happens on the transition from 1111111111 to 0000000000. Most counts settle far faster, but the clock period must accommodate the worst case, so $t_{total}=N\times t_{pd}$ with $N=10$.

Contrast with a synchronous counter built from the same flip-flops: all stages are clocked together, so $t_{total}=t_{pd}+t_{gate}\approx 20\text{ ns}$ regardless of width, giving roughly 50 MHz — ten times faster. Stating this comparison answers the implicit “so why use synchronous?” and is worth marks in a 13-mark question.

Unit discipline: convert nanoseconds to seconds before inverting. $1/200\text{ ns}$ is 5 MHz, not 5 Hz or 5 GHz.

3. Truncated Ripple Counters (MOD-N / Decade Counter)

A full N-bit counter has a natural modulus of 2ᴺ. A Truncated Counter resets to 0000 before reaching 2ᴺ - 1 by decoding a specific terminal state using a feedback NAND gate connected to the asynchronous CLR̅ (Clear) inputs.

3.1 Design of a BCD / Decade Ripple Counter (MOD-10)

To count from 0000 (0) to 1001 (9) and reset at 1010 (10):

1. Target Terminal Count: 10₁₀ = 1010₂ (Q₃ Q₂ Q₁ Q₀ = 1010).

2. NAND Decoding Logic: Decode Q₃ = 1 and Q₁ = 1: CLR̅ = ̅(Q₃ · Q₁)

3. Operation: As soon as state 1010 (10) is momentarily reached, the NAND output drops to 0, asynchronously clearing all 4 flip-flops back to 0000 in a fraction of a nanosecond.

 Q3 -----\

[ NAND ]---⇒ Active-LOW Clear (CLR) to all 4 Flip-Flops

Q1 -----/

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