Related Concepts: 6.03 Synchronous Counter Design (Sequence, Code & BCD Counters) | 6.02 Asynchronous (Ripple) Counters & Propagation Delay Calculations | 6.01 Registers, Parallel Load & Shift Register Dynamics

6.04 Specialized Counters (Up-Down, Johnson, Ring & Mod-N ICs)

Two reliable questions live here

Question	Appearances	Marks
4-bit synchronous binary up-down counter (usually bundled with “What is a ripple counter?“)	5 (2018, 2021, 2022, 2023, 2025)	5–10
Johnson counter with 10 timing signals	4 (2015, 2018, 2019, 2025)	9–10

Beyond standard binary counters, practical digital systems employ specialized counter topologies: Up-Down Counters for reversible position tracking, Ring & Johnson Counters for multi-phase timing signal generation, and Parallel-Load IC Counters (such as the 74161/74163) for modular MOD-N frequency division.

1. Synchronous Binary Up-Down Counter

Exam Problem (PYQ 2018, 2022, 2023 — 10 marks; 2025 — 09 marks; 2021 — 05 marks)

Question (verbatim, 2022/2023): What is ripple counter? Draw the diagram of a 4-bit synchronous binary up-down counter.

Two halves — the ripple-counter definition is in 6.02 Asynchronous (Ripple) Counters & Propagation Delay Calculations. The 2021 version (5 marks) drops it and asks only for the diagram.

A 4-bit synchronous up-down counter counts up ($0\to 15$) when control $U=1$, and down ($15\to 0$) when $U=0$.

1.1 The Governing Rule

• Counting up: bit $i$ toggles when all lower bits are 1
• Counting down: bit $i$ toggles when all lower bits are 0

1.2 Steering Logic Equations

Using T flip-flops $A_3{A}_2{A}_1{A}_0$ ($A_0$ = LSB) with control $U$:

$T_0=1$ $T_1=U{A}_0+U^{\prime }{A}_0^{\prime }$ $T_2=U{A}_1{A}_0+U^{\prime }{A}_1^{\prime }{A}_0^{\prime }$ $T_3=U{A}_2{A}_1{A}_0+U^{\prime }{A}_2^{\prime }{A}_1^{\prime }{A}_0^{\prime }$

The complements are the whole point

Each equation is a pair of terms: the up-condition ANDed with $U$, plus the complemented down-condition ANDed with $U^{\prime }$. Writing $T_1=U{A}_0+U{A}_0$ (identical terms, no primes) collapses to $U{A}_0$ and the counter loses its down-count entirely.

Quick check: at state 0000 counting down ($U=0$): $T_0=1$, $T_1=0+1\cdot 1=1$, $T_2=1$, $T_3=1$ — all four toggle, giving 1111 $=15$. Correct wrap-around for a down-counter ✓

And counting up from 1111 ($U=1$): all four conditions are satisfied, all toggle, giving 0000 ✓

Each $T_i$ therefore needs one AND gate for the up-path, one for the down-path, and an OR gate to combine them.

 Up Line ----⇒[ AND 1 ]----\

[ OR ]---⇒ T1 Drive Logic

Down Line —⇒[ AND 2 ]----/



2. Ring Counter vs. Johnson Counter

Both Ring and Johnson counters are constructed from shift registers with feedback from the last stage to the first stage.

2.1 Ring Counter (Direct Feedback)

• Architecture: N-bit shift register with the serial output QN-1 connected directly back to the serial input D0.
• Initial State: Preset with a single 1 bit (e.g. 1000).
• Number of Unique States / Timing Signals: Exactly N states for N flip-flops.
• 4-Bit Sequence: 1000 → 0100 → 0010 → 0001 → 1000.

2.2 Johnson Counter (Twisted-Ring / Switch-Tail Counter)

• Architecture: N-bit shift register with the inverted output QN-1 connected back to serial input D0.
• Initial State: Cleared to all zeros (0000).
• Number of Unique States / Timing Signals: Exactly 2N states for N flip-flops.

4-Bit Johnson Counter State Sequence (N=4 ⇒ 8 States)

Clock pulse	$Q_3$	$Q_2$	$Q_1$	$Q_0$	Decoded timing signal
0	0	0	0	0	$T_0=Q_3^{\prime }{Q}_0^{\prime }$
1	1	0	0	0	$T_1=Q_3{Q}_2^{\prime }$
2	1	1	0	0	$T_2=Q_2{Q}_1^{\prime }$
3	1	1	1	0	$T_3=Q_1{Q}_0^{\prime }$
4	1	1	1	1	$T_4=Q_3{Q}_0$
5	0	1	1	1	$T_5=Q_3^{\prime }{Q}_2$
6	0	0	1	1	$T_6=Q_2^{\prime }{Q}_1$
7	0	0	0	1	$T_7=Q_1^{\prime }{Q}_0$

Every decoding term needs exactly one complement

Each timing signal is a 2-input AND of one true and one complemented output. Dropping the primes makes $T_0=T_4$, $T_1=T_5$, $T_2=T_6$ and $T_3=T_7$ — each gate would then fire in two states instead of one, and the decoder is useless.

How to build each term without memorising the table: find the single 1→0 or 0→1 boundary in the state’s bit pattern and AND the two bits either side of it. State 2 is 1100: the boundary is between $Q_2$ (=1) and $Q_1$ (=0), so $T_2=Q_2{Q}_1^{\prime }$. The two all-same states (0000 and 1111) have no internal boundary, so they use the wrap-around pair $Q_3$ and $Q_0$.

Self-check: substitute any state into all eight expressions — exactly one must be 1. For state 5 (0111): $T_5=Q_3^{\prime }{Q}_2=1\cdot 1=1$ ✓, and every other term evaluates to 0.

Advantage of Johnson Counter over Ring Counter: A Johnson counter generates 2N distinct timing signals using only N flip-flops and 2-input AND decoding gates, whereas a Ring counter requires 2N flip-flops to generate 2N timing signals.

2.3 Comprehensive Counter Comparison Table

Feature	Standard Binary Counter	Ring Counter	Johnson (Twisted-Ring) Counter
Flip-flops needed for $M$ states	$\lceil {\log }_{2}M\rceil$	$M$	$M/2$
States from $N$ flip-flops	$2^N$	$N$	$2N$
Decoding Logic Complexity	High (N-input AND gates required per state).	None (Outputs Qi are directly timing signals).	Low (2-input AND gates required per state).
Self-Starting Ability	Self-starting.	Requires initial preset (1000).	Self-starting / easily initialized (0000).

3. MOD-N Counter Design Using Parallel-Load ICs

Exam Problem (PYQ 2017 — 12 marks; 2021 — 13 marks)

Question (verbatim): Design a Mod-6 counter using a counter with parallel load.

The phrase “with parallel load” points you at Method 2 below — the examiner wants the LOAD-input technique, not a CLEAR-pin trick.

Integrated Circuit counters (such as the 74161 4-bit binary counter) feature synchronous parallel load inputs (D3 D2 D1 D0), a load enable line (LOAD), and a ripple carry output (RCO).

3.1 Design Methodology for MOD-N Counter using 74161 IC

To design a MOD-6 counter (0 → 5) using a 74161 IC:

1. Method 1 (NAND Clear Feedback): Decode terminal state 510 = 01012 (Q2 · Q0) using a NAND gate connected to active-LOW CLEAR.
2. Method 2 (Parallel Load Preset) — the method the question asks for: tie the parallel inputs $D_3{D}_2{D}_1{D}_0$ to 0000. Connect the active-LOW $\overline{LOAD}$ pin to a NAND gate decoding the terminal state $5=0101_2$, i.e. $\overline{LOAD}=\overline{Q_2{Q}_0}$. On reaching state 5 the NAND output goes LOW, so the next clock edge loads 0000 instead of incrementing. The counter therefore cycles $0,1,2,3,4,5,0,\dots$ — six states.

Load is synchronous; Clear is usually asynchronous

This distinction decides which state you decode:

• Synchronous LOAD (Method 2): decode the last state you want to keep — here 5. The reset happens on the next clock edge, so state 5 is fully displayed.
• Asynchronous CLEAR (Method 1): decode one past the last wanted state — here 6 — because clear acts immediately. State 6 appears as a brief glitch before being wiped.

Decoding 5 with an asynchronous clear gives a MOD-5 counter, not MOD-6. Since the question specifies “a counter with parallel load”, use Method 2 and decode 5.

General rule: for MOD-$N$ starting at 0 with synchronous load, decode state $N-1$.

4. Past Year Master Questions & Solutions

Major Exam Problem (PYQ 2015, 2018, 2019 — 10 marks; 2025 — 09 marks)

Question (verbatim): Construct a Johnson counter with ten timing signals.

Step 1 — Flip-Flop Count

A Johnson counter of $N$ flip-flops produces $2N$ distinct states:

$2N=10⟹\mathbf{N}=5\text{ flip-flops}$

(A ring counter would need 10 flip-flops for the same job — that comparison is worth stating.)

Step 2 — State Table

Five flip-flops $Q_4{Q}_3{Q}_2{Q}_1{Q}_0$, shift right, with the inverted output $Q_0^{\prime }$ fed back to the serial input:

Pulse	$Q_4$	$Q_3$	$Q_2$	$Q_1$	$Q_0$	Decoded signal
0	0	0	0	0	0	$T_0=Q_4^{\prime }{Q}_0^{\prime }$
1	1	0	0	0	0	$T_1=Q_4{Q}_3^{\prime }$
2	1	1	0	0	0	$T_2=Q_3{Q}_2^{\prime }$
3	1	1	1	0	0	$T_3=Q_2{Q}_1^{\prime }$
4	1	1	1	1	0	$T_4=Q_1{Q}_0^{\prime }$
5	1	1	1	1	1	$T_5=Q_4{Q}_0$
6	0	1	1	1	1	$T_6=Q_4^{\prime }{Q}_3$
7	0	0	1	1	1	$T_7=Q_3^{\prime }{Q}_2$
8	0	0	0	1	1	$T_8=Q_2^{\prime }{Q}_1$
9	0	0	0	0	1	$T_9=Q_1^{\prime }{Q}_0$

After pulse 9 the feedback $Q_0^{\prime }=0$ returns the counter to 00000 and the cycle repeats.

Step 3 — Circuit

Five D flip-flops in a shift-right chain on a common clock, with $\overline{Q_0}$ wired back to $D_4$, plus ten 2-input AND gates implementing the decoding column above.

What earns full marks here

Three deliverables: the flip-flop count with its justification ($2N=10$), the 10-row state table, and the 10 decoding expressions. Many answers give the table and stop — the decoding gates are what make them timing signals rather than just states, and they are typically half the marks.

Add one line of comparison — “a ring counter would require 10 flip-flops for the same 10 signals, but needs no decoding gates” — to show you understand the trade-off.