05 Chapter Map - Sequential Logic & Flip-Flops
Chapter 5 Overview & Map of Content (MOC)
Combinational vs sequential logic, SR and JK latches and flip-flops, D and T variants, master-slave triggering and the race-around condition, flip-flop conversions, synchronous circuit analysis and synthesis, and state reduction.
📚 Study Notes Index
| # | Note | What it covers | PYQ years | Typical marks |
|---|---|---|---|---|
| 5.01 | 5.01 Sequential Logic Fundamentals, Latches & Flip-Flops (SR & JK) | Characteristic & excitation tables, one-bit memory, combinational vs sequential, state terminology | 2015–2025 (every paper) | 8–13 |
| 5.02 | 5.02 Flip-Flop Variants (Master-Slave JK, T & D Flip-Flops) & Triggering Mechanics | D edge-triggered operation, T flip-flop, race-around, master-slave JK | 2015–2022 | 8–12 |
| 5.03 | 5.03 Flip-Flop Conversions & Functional Transformation Mechanics | SR↔JK, JK→D, JK→T conversions | 2017, 2018, 2023, 2024, 2025 | 9–12 |
| 5.04 | 5.04 Synchronous Sequential Circuit Analysis & Synthesis | State table from circuit, synthesis from state equations, serial adder | 2015–2022, 2024, 2025 | 10–12 |
| 5.05 | 5.05 State Reduction Algorithms & Output Sequence Analysis | State reduction, output sequence tracking, state assignment | 2015, 2016, 2018, 2022–2025 | 5–15 |
| 5.06 | 5.06 Chapter 5 Master PYQ Solutions & Synthesis Puzzles | Additional worked sequential problems | — | — |
🎯 Exam Weight
Ranked by appearances
Rank Question Appearances Marks Note 1 Characteristic + excitation tables of RS, JK, D, T 8 10–12 5.01 Sequential Logic Fundamentals, Latches & Flip-Flops (SR & JK) §5 2 State table & diagram from a given circuit 6 10–12 5.04 Synchronous Sequential Circuit Analysis & Synthesis §2 2 State reduction / design from reduced table 6 5–15 5.05 State Reduction Algorithms & Output Sequence Analysis 4 D-type edge-triggered operation 5 8–12 5.02 Flip-Flop Variants (Master-Slave JK, T & D Flip-Flops) & Triggering Mechanics §1 5 One-bit memory + combinational vs sequential 4 10–12 5.01 Sequential Logic Fundamentals, Latches & Flip-Flops (SR & JK) §1 5 State table / diagram / equation definitions 4 8–10 5.01 Sequential Logic Fundamentals, Latches & Flip-Flops (SR & JK) §2 7 Race-around condition and its fix 3 10 5.02 Flip-Flop Variants (Master-Slave JK, T & D Flip-Flops) & Triggering Mechanics §3 Chapter 5 supplies roughly 35–45 marks per paper — the largest single block in Instructor 2’s half.
The excitation table is the hinge of the whole course
Everything downstream — every sequential design in this chapter, every counter in 06 Chapter Map - Registers & Counters — starts by looking up “what inputs produce this state change?” Memorise all four excitation tables (5.01 §5) and a third of both chapters becomes mechanical.
Distinctions that decide whole answers
- Characteristic vs excitation table. Characteristic = inputs → next state (analysis). Excitation = required change → inputs (design). The 8-appearance question asks for both.
- Analysis vs synthesis direction. Analysis: circuit → state table. Synthesis: specification → circuit. Check which way the question runs.
- “Reduce” vs “design the reduced form.” From 2022 the state-reduction question says design, which adds state assignment, excitation table, K-maps and schematic — roughly triple the work. See 5.05 State Reduction Algorithms & Output Sequence Analysis §4A.
- Tying JK inputs together gives T, not D. A D flip-flop needs , — through an inverter.
🔗 Related Resources
- Course Teaching Plan: ECE 2103 - Digital Electronics and Logic Circuits
- Instructor: Foysal Sir (Instructor 2), Weeks 1–4
- Next chapter: 06 Chapter Map - Registers & Counters — every counter design depends on the excitation tables here
- Lab tie-in (ECE 2104): Week 6 verifies flip-flop circuits.