Related Concepts: 5.01 Sequential Logic Fundamentals, Latches & Flip-Flops (SR & JK) | 5.03 Flip-Flop Conversions & Functional Transformation Mechanics | 5.05 State Reduction Algorithms & Output Sequence Analysis

5.04 Synchronous Sequential Circuit Analysis & Synthesis

Analysis appears six times; synthesis three

• Analysis — “write down the state table and draw the state diagram of the following sequential circuit” — 2015, 2016, 2019, 2020, 2021, 2022 (10–12 marks). Always figure-based.
• Synthesis — design a circuit from given state equations or a state diagram — 2017, 2024, 2025 (12 marks).

The two run in opposite directions: analysis goes circuit → equations → state table → diagram; synthesis goes specification → state table → excitation table → K-maps → circuit.

Overview: The study of clocked sequential circuits involves two complementary procedures: Analysis (extracting state tables and state diagrams from a given logic schematic) and Synthesis (designing a gate-level logic schematic from verbal specifications, state equations, or state diagrams).

1. Mealy vs. Moore State Machine Models

Clocked sequential circuits are categorized based on how output signals are generated:

1.1 Structural Comparison

Feature	Mealy Machine	Moore Machine
Output Dependency	Function of Present Inputs AND Present State (Y = f(X, Q)).	Function of Present State ONLY (Y = f(Q)).
State Diagram Labels	Arcs labeled as Input / Output (X / Y).	State nodes labeled as State / Output (Q / Y).
Number of States	Requires fewer states for a given specification.	Requires more states (or equal) compared to Mealy.
Response Speed	Output changes asynchronously with input changes during active state.	Output changes synchronously strictly at active clock edge.
Glitch Susceptibility	Higher (input glitches propagate directly to output).	Lower (output is isolated from input glitches by state registers).

2. Analysis Algorithm for Clocked Sequential Circuits

Step 1: Extract Flip-Flop Input Equations & Output Equations from Schematic

Step 2: Substitute Input Equations into FF Characteristic Equations to get State Equations Q(t+1)

Step 3: Construct State Table for all Input/State combinations

Step 4: Draw State Diagram with Node Transitions

2.1 Master Analysis Example

Given Circuit Equations:

• Flip-Flop A (JK type): J_A = x · B, K_A = x’
• Flip-Flop B (JK type): J_B = x’, K_B = A ⊕ x
• Output Equation: Y = A · B · x

Step 1: Derive Next-State Equations

1. For Flip-Flop A (A_{t+1}): A_{t+1} = J_A A’ + K_A’ A = (xB)A’ + (x’)‘A = xA’B + xA = x(A + B)

2. For Flip-Flop B (B_{t+1}): B_{t+1} = J_B B’ + K_B’ B = (x’)B’ + (A ⊕ x)‘B

Step 2: Construct the State Table

Present State (A B)	Input (x)	Next State (A_{t+1} B_{t+1})	Output (Y)
0 0	0	0 1	0
0 0	1	0 0	0
0 1	0	0 1	0
0 1	1	1 0	0
1 0	0	0 0	0
1 0	1	1 1	0
1 1	0	0 0	0
1 1	1	1 0	1

3. Synthesis Algorithm for Clocked Sequential Circuits

Step 1: State Diagram / Verbal Spec

Step 2: State Table & Excitation Table Mapping

Step 3: K-Map Simplification for FF Drive Logic

Step 4: Draw Logic Diagram

3.1 Design Example: Synthesis from State Equations

Design Task: Synthesize a sequential circuit using D flip-flops for state equations: A_{t+1} = x A B + y A’ C + x y; B_{t+1} = x A’ + B C’

Synthesis Solution: Since the characteristic equation of a D flip-flop is Q_{n+1} = D, the required flip-flop input logic is obtained directly: D_A = x A B + y A’ C + x y; D_B = x A’ + B C’.

Implementation: Drive input D_A with a 3-input OR gate fed by AND terms (xAB), (yA’C), and (xy). Drive input D_B with a 2-input OR gate fed by (xA’) and (BC’).

4. Sequential Serial Adder Design

Exam Problem (PYQ 2019 — 10 marks)

Question (verbatim): Design a serial adder using a sequential logic procedure.

The phrase “using a sequential logic procedure” means: do not just draw a full-adder with a shift register. Treat the carry as the machine’s state (two states: carry = 0, carry = 1), build the state table, derive the flip-flop excitation, and produce the circuit — i.e. apply the synthesis algorithm in §3.

A Serial Adder adds two multi-bit binary numbers bit-by-bit sequentially using a single Full Adder circuit and a D flip-flop to store the carry bit between clock cycles.

4.1 State & Excitation Table for Serial Adder

Let Q_n be the present carry stored in the D flip-flop. Inputs are A and B.

Inputs (A B)	Present Carry (Q_n)	Next Carry (Q_{n+1} = D)	Sum Output (S)
0 0	0	0	0
0 0	1	0	1
0 1	0	0	1
0 1	1	1	0
1 0	0	0	1
1 0	1	1	0
1 1	0	1	0
1 1	1	1	1

4.2 Derived Logic Equations

• Sum Equation: S = A ⊕ B ⊕ Q_n
• Carry (Flip-Flop Input) Equation: D = A B + A Q_n + B Q_n

5. Past Year Questions (PYQs)

PYQ Index for this note

Question (as asked)	Years	Marks	Solved in
Write down the state table and draw the state diagram of the following sequential circuit (figure)	2015, 2019 (12), 2020 (10)	10–12	§2
What is sequential circuit? Write the state table and draw the state diagram (figure)	2016	10	§2, and 5.01 Sequential Logic Fundamentals, Latches & Flip-Flops (SR & JK) §1
Define state table, state diagram and state equation. Obtain the state table of the circuit in figure 7(b)	2021	10	§2, and 5.01 Sequential Logic Fundamentals, Latches & Flip-Flops (SR & JK) §2
Analyze the circuit in Figure 6(b); write the state table and state diagram	2022	12	§2
A sequential circuit has one input and one output; the state diagram is given. Design it with T flip-flops	2017	12	§3
Design a sequential circuit described by the state equations $A(t+1)=xAB+y{A}^{\prime }C+xy$, $B(t+1)=xAC+y{B}^{\prime }{C}^{\prime }$, $C(t+1)=x^{\prime }B+y{A}^{\prime }{B}^{\prime }$ using JK flip-flops	2024, 2025	12	§3.1
Design a serial adder using a sequential logic procedure	2019	10	§4

Pattern to notice: analysis appears in six of the last eleven papers and is always attached to a figure, so the marks depend on correctly reading gate connections and writing the flip-flop input equations. Once you have those, the state table is mechanical.

Watch for the reversed direction. The 2024/2025 synthesis question hands you the state equations directly — no figure, no reduction — so you skip straight to the excitation table. Do not confuse it with the state-reduction design questions in 5.05 State Reduction Algorithms & Output Sequence Analysis, which start from a redundant state table.

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6. Legacy Worked Questions

PYQ Master Problem (2019): Serial Adder Synthesis. Question: Design a Serial Adder using a sequential logic procedure. Show state table, logic equations, and block diagram. [8 Marks]

Solution:

1. System Definition: State that a serial adder requires 1 Full Adder + 1 D Flip-Flop for carry storage.

2. State Table: Draw the 8-row table mapping inputs A, B and carry Q_n to Sum S and Next Carry D.

3. Logic Expressions: S = A ⊕ B ⊕ Q_n and D = AB + BQ_n + AQ_n.

4. Block Diagram: Draw Full Adder block connected to D Flip-Flop feedback path.