Related Concepts: 5.01 Sequential Logic Fundamentals, Latches & Flip-Flops (SR & JK) | 5.03 Flip-Flop Conversions & Functional Transformation Mechanics | 5.04 Synchronous Sequential Circuit Analysis & Synthesis

5.02 Flip-Flop Variants (Master-Slave JK, T & D Flip-Flops) & Triggering Mechanics

Three recurring questions live here

Question	Appearances	Marks
Show the operation of the D-type edge-triggered flip-flop with necessary diagram	5 (2015, 2016, 2017, 2019, 2022)	8–12
Why does race-around occur in JK flip-flops? How is it resolved?	3 (2017, 2020, 2021)	10
Draw the logic diagram of a clocked master-slave JK flip-flop	2 (2015, 2019)	8–10

The race-around and master-slave questions are two halves of one story — master-slave is the answer to race-around, so revise them together.

Overview

While basic SR and JK flip-flops provide foundation logic, practical digital circuits require specialized variants: the D (Data/Delay) Flip-Flop for temporary buffer storage, the T (Toggle) Flip-Flop for binary counters, and the Master-Slave JK Flip-Flop to resolve the severe physical limitation known as the Race-Around Condition.

1. D-Type (Data / Delay) Flip-Flop

Major Exam Problem (PYQ 2015, 2017, 2019 — 10 marks; 2016 — 08 marks; 2022 — 12 marks)

Question (verbatim): Show the operation of the D-type edge-triggered flip-flop with necessary diagram.

Note the word “edge-triggered” — the marks are not just for the characteristic table. A full answer needs: the logic diagram, the characteristic table and equation $Q_{n+1}=D$, an explanation of what edge triggering means (the output samples $D$ only during the active clock transition, not the whole clock level), and ideally a timing waveform showing $Q$ following $D$ one clock later.

The D flip-flop is derived from the SR flip-flop by inserting an inverter between the S and R inputs (S = D and R = NOT D), ensuring that S and R are never simultaneously equal to 1.

1.1 Logic Schematic & Characteristic Derivation

 +-------+

D ----| |---⇒ S -⇒[ Gated SR Latch ]---⇒ Q

| | NOT |

+⇒| Gate |---⇒ R

+-------+

Characteristic Table & Equation Derivation

D	Qn	Qn+1	Operation / State
0	0	0	Reset
0	1	0	Reset
1	0	1	Set
1	1	1	Set

Substituting S = D and R = NOT D into Qn+1 = S + (NOT R)Qn:

Qn+1 = D + NOT(NOT D)Qn = D + D · Qn = D(1 + Qn) = D

Qn+1 = D

Key Result: The Delay Property

The next state Qn+1 is strictly equal to the input D during the active clock edge. Thus, data at input D is delayed by exactly one clock period before appearing at output Q.

2. T-Type (Toggle) Flip-Flop

The T flip-flop is derived from the JK flip-flop by tying the J and K inputs together to a single terminal T (J = T and K = T).

2.1 Logic Schematic & Characteristic Equation

Substitute J = T and K = T into Qn+1 = J(NOT Qn) + (NOT K)Qn:

Qn+1 = T(NOT Qn) + (NOT T)Qn = T XOR Qn

Characteristic Table & Excitation Table

T	Qn	Qn+1	Operation
0	0	0	No Change (Hold)
0	1	1	No Change (Hold)
1	0	1	Toggle
1	1	0	Toggle

3. The Race-Around Condition in JK Flip-Flops

Major Exam Problem (PYQ 2017, 2020, 2021 — 10 marks)

Question (verbatim, 2021): Why does race around condition occur in JK flip-flop? How can this problem be resolved?

Both halves carry marks. “Why” needs the $J=K=1$ toggle-during-a-wide-clock-pulse mechanism; “how” needs at least one of the three fixes in §3.2 — the strongest answer names master-slave (§4) and explains why splitting the latch into two stages prevents the output feeding back within one clock period.

3.1 Definition & Physical Cause

Definition of Race-Around Condition [PYQ: 2017, 2020, 2021]

In a level-triggered JK flip-flop, if J = 1 and K = 1 while the clock pulse remains HIGH (CLK = 1) for a duration tp that is longer than the propagation delay of the gates tpd (tp > tpd), the output Q will toggle continuously back and forth (0 → 1 → 0 → 1 …) during the clock pulse width. At the end of the clock pulse, the final state of Q becomes unpredictable and uncertain. This physical defect is called the Race-Around Condition.

Clock Pulse (CLK): +------+ +------+

| tp | | |

+------+ +------+

Output Q (t_p > t_pd):

|-| |-| |-|

| |__| |__| |___ (Continuous Toggling / Racing)

3.2 Methods to Eliminate the Race-Around Condition

1. Keep tp < tpd: Make the clock pulse width tp smaller than the propagation delay tpd of the gates. (Impractical in high-speed IC manufacturing).
2. Edge-Triggering: Use edge-triggered flip-flops (transitional RC differentiating circuits) so triggering occurs strictly at the edge instant.
3. Master-Slave Architecture: Use a Master-Slave JK Flip-Flop setup where clock inversion isolates input sampling from output updates.

4. Clocked Master-Slave JK Flip-Flop

Exam Problem (PYQ 2015 — 10 marks; 2019 — 08 marks)

Question (verbatim, 2019): Draw the diagram of clocked master-slave JK flip-flop using NAND gates.

The 2019 wording specifies NAND gates — draw the gate-level implementation, not a block diagram of two boxes labelled “master” and “slave”. The 2015 version says only “logic diagram”, so either is acceptable there.

4.1 Circuit Architecture

A Master-Slave JK Flip-Flop consists of two clocked SR/JK latches connected in series:

1. Master Stage: Clocked directly by CLK.
2. Slave Stage: Clocked by the inverted clock signal NOT CLK.

 +-----------------------+ +-----------------------+

| MASTER LATCH | | SLAVE LATCH |

J -⇒| NAND 3 NAND 1 |---⇒ NAND 7 NAND 5 |---⇒ Q ----+

CLK ⇒| (CLK) | Y | (CLK’) | |

Q’ ⇒| NAND 4 NAND 2 |---⇒ NAND 8 NAND 6 |---⇒ Q’—+ |

+-----------------------+ Y’ +-----------------------+ | |

^ ^ ^ ^ | |

K -------|---------------+ | | | |

| | | | |

+--------------[ NOT Gate ]---+ | | |

| (CLK’) | | |

+---------------------------------------------|----------------+ |

| | |

+---------------------------------------------+------------------+

4.2 Operational Walkthrough

1. When CLK = 1 (NOT CLK = 0): The Master is ENABLED. Inputs J and K update intermediate outputs Y and Y’. The Slave is DISABLED. Output Q remains unchanged.
2. When CLK transitions from 1 → 0 (NOT CLK = 1): The Master becomes DISABLED, locking inputs Y and Y’. The Slave becomes ENABLED, copying intermediate signals Y and Y’ to final outputs Q and Q’.
3. Why it eliminates Race-Around: Since Master and Slave are never active at the same time, feedback from Q cannot return to input gates while output is updating. Toggling occurs at most once per clock cycle.

5. Summary & Comparison of All 4 Primary Flip-Flops

Flip-Flop	Inputs	Char. Equation	Excit (0-0)	Excit (0-1)	Excit (1-0)	Excit (1-1)
SR	S, R	Qn+1=S+(NOT R)Qn	S=0, R=X	S=1, R=0	S=0, R=1	S=X, R=0
JK	J, K	Qn+1=J(NQn)+(NK)Qn	J=0, K=X	J=1, K=X	J=X, K=1	J=X, K=0
D	D	Qn+1=D	D=0	D=1	D=0	D=1
T	T	Qn+1=T XOR Qn	T=0	T=1	T=1	T=0

6. Past Year Master Questions & Solutions

PYQ Master Problem (2017, 2020, 2021): Race-Around Condition & Master-Slave

Question: What is the “Race-around condition” in JK flip-flops? Why does it occur, and how is it resolved using a Master-Slave arrangement? [8 Marks]

Solution:

1. Definition & Cause: Refer to Section 3.1. State the inequality tp > tpd where clock pulse width exceeds logic gate delay.
2. Master-Slave Architecture: Draw the two-stage Master-Slave schematic (Section 4.1).
3. Operation & Isolation Proof: Explain that during CLK=1, Master accepts J,K inputs while Slave is isolated. At CLK → 0, Master shuts off and Slave passes state to Q. Because output feedback cannot re-enter the Master while the Slave is updating, the circuit toggles exactly once, successfully eliminating race-around.