Related Concepts: 5.01 Sequential Logic Fundamentals, Latches & Flip-Flops (SR & JK) | 5.02 Flip-Flop Variants (Master-Slave JK, T & D Flip-Flops) & Triggering Mechanics | 5.08 Flip-Flop Mathematical Derivations & Transformation Proofs

5.07 Sequential Architecture, Triggering Mechanics & Race-Around Analysis

Overview

Sequential circuits combine combinational logic with memory storage elements in a closed feedback loop. Understanding the internal gate-level construction of edge-triggered devices, clock setup/hold windows, and eliminating the unstable Race-Around Condition via Master-Slave architectures is fundamental to digital system design.

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1. Generic Sequential Circuit Architecture [PYQ: 2017, 2019]

A sequential circuit consists of a Combinational Logic Block and Memory Elements (latches or flip-flops) connected in a closed feedback loop.

 +---------------------------------------+

| COMBINATIONAL LOGIC BLOCK |

External Inputs -⇒| |-⇒ External Outputs

X(t) | Next-State Equations Y(t) = f(X, Q) | Z(t) = g(X, Q)

+---------------------------------------+

| ^

| Next State | Present State

v Y(t) | Q(t)

+---------------------------------------+

| MEMORY ELEMENTS |

System Clock ----⇒| (Flip-Flops / Latches) |

CLK +---------------------------------------+



1.1 Structural Components

• 1. Inputs $X(t)$: External digital signals applied to the circuit.
• 2. Combinational Logic: Computes next-state signals $Y(t)$ and external outputs $Z(t)$.
• 3. Memory Elements: Array of flip-flops storing the present state $Q(t)$.
• 4. Feedback Path: Returns $Q(t)$ to combinational inputs, establishing memory hysteresis.
• 5. Clock Line ($CLK$): Synchronizes state updates across all memory elements.

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2. Clock Triggering Mechanics & Setup/Hold Windows

Triggering Mode	Waveform Condition	Operational Behavior
Active-HIGH Level	$CLK=1$	Output continuously tracks inputs while clock is HIGH.
Active-LOW Level	$CLK=0$	Output continuously tracks inputs while clock is LOW.
Positive Edge (Rising)	$CLK\uparrow (0\to 1)$	Output transitions strictly at the rising edge instant.
Negative Edge (Falling)	$CLK\downarrow (1\to 0)$	Output transitions strictly at the falling edge instant.

2.1 Setup ($t\_su$) and Hold ($t\_h$) Time Constraints

Key Exam Checkpoint: Timing Windows

* Setup Time ($t\_su$): Minimum time data input $D$ must remain stable BEFORE the active clock edge.

* Hold Time ($t\_h$): Minimum time data input $D$ must remain stable AFTER the active clock edge.

* Violation Result: Entering a metastable state where output oscillates unpredictably between $0$ and $1$.

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3. Internal Gate-Level Construction of Edge-Triggered D Flip-Flop [PYQ: 2015, 2016, 2017, 2019, 2022]

An edge-triggered D flip-flop uses three interconnected NAND-gate latches to sample input $D$ strictly during the rising edge of $CLK$.

 +------------+

D —⇒| NAND 1 |----+

| | | +------------+

CLK -⇒| NAND 2 |----+⇒| NAND 3 |---⇒ Output Q

+------------+ | (SR Latch) |

| +------------+

v ^

+------------+ |

| NAND 4 |--------------+---⇒ Output Q’

+------------+

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3.1 Operational Phases

• 1. $CLK=0$: Gates 2 and 3 outputs are held at logic $1$. The output SR latch holds its previous state $Q$.
• 2. $CLK\uparrow (0\to 1)$ Transition: Gate 2 output drops to $0$ if $D=1$, setting output $Q\to 1$. Gate 4 output drops to $0$ if $D=0$, resetting output $Q\to 0$.
• 3. $CLK=1$ (Level Held): Gate 2 or 4 locks out further changes in $D$, rendering the device immune to input noise until the next clock edge.

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4. In-Depth Race-Around Condition Analysis [PYQ: 2017, 2020, 2021]

4.1 The Timing Inequality

In a level-triggered JK flip-flop, setting $J=1,K=1$ causes output $Q$ to toggle ($Q\_n+1=\overline{Q\_n}$). If clock pulse width $t\_p$ exceeds propagation delay $t\_pd$:

$t\_pd<t\_p<T$

Output $Q$ toggles continuously ($0\to 1\to 0\to 1\dots$) during $t\_p$. The state when $CLK$ falls to $0$ is unpredictable.

4.2 Methods of Elimination

• 1. Propagation Delay Increase: Ensure $t\_p<t\_pd$ *(unrealistic in high-speed systems)*.
• 2. Edge-Triggering: Sample inputs strictly at edge transitions.
• 3. Master-Slave Architecture: Isolate input sampling from output updates using dual cross-coupled latches.

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5. Master-Slave JK Flip-Flop NAND Logic Schematic [PYQ: 2015, 2019]

 +-----------------------+ +-----------------------+

| MASTER LATCH | | SLAVE LATCH |

J -⇒| NAND 3 NAND 1 |---⇒ NAND 7 NAND 5 |---⇒ Q ----+

CLK ⇒| (CLK) | Y | (CLK’) | |

Q’ ⇒| NAND 4 NAND 2 |---⇒ NAND 8 NAND 6 |---⇒ Q’—+ |

+-----------------------+ Y’ +-----------------------+ | |

^ ^ ^ ^ | |

K -------|---------------+ | | | |

+--------------[ NOT Gate ]---+ | | |

(CLK’) +----------------+ |

|



5.1 Step-by-Step Operation Proof

• * $CLK=1$ ($\overline{CLK}=0$): Master latch active; $Y,Y^{\prime }$ update based on $J,K$. Slave latch isolated ($CL{K}^{\prime }=0$). Output $Q$ remains constant.
• * $CLK\downarrow (1\to 0)$ ($\overline{CLK}=1$): Master latch turns OFF; Slave latch turns ON, loading $Y,Y^{\prime }$ to final output $Q$. Since Master is OFF, output $Q$ cannot feed back to change $Y$, eliminating race-around completely.