7.02 Semiconductor & Magnetic Memory Systems

Overview

Memory systems store binary information in arrays of memory cells, characterised by access speed, density, power and volatility. This note covers the two topics the examiner actually asks about — magnetic core memory and EPROM/E²PROM — plus the supporting classification background.

Two of the most repeated questions in the whole course live here

Question Appearances Marks
Magnetic core memory — information transfer during write (and read) 8 (2015, 2016, 2018, 2019, 2020, 2021, 2022, 2023) 8–12
Write short notes on EPROM and E²PROM 10 (2015–2019, 2021–2025) 5–10

Between them, roughly 20 marks in essentially every paper. Both are descriptive — no derivation, no circuit analysis.

Question	Appearances	Marks
Magnetic core memory — information transfer during write (and read)	8 (2015, 2016, 2018, 2019, 2020, 2021, 2022, 2023)	8–12
Write short notes on EPROM and E²PROM	10 (2015–2019, 2021–2025)	5–10

1. Memory Fundamentals

Memory cell — the basic 1-bit bistable storage element.
Memory word — a group of $M$ bits addressed and transferred together.
Address lines ( $K$ ) — $K$ address lines select $2^{K}$ distinct locations.
Data lines ( $M$ ) — bidirectional lines carrying data in or out.

$Capacity (bits) = 2^{K} \times M$

Example: 12 address lines and 8 data lines give $2^{12} = 4096$ words $\times$ 8 bits $= 32, 768$ bits $= 4$ KB.

Definition Question (asked as the opening clause of the magnetic core question in 2015, 2018, 2019, 2020, 2022, 2023)

“What is memory element?” / “Define memory element.”

A memory element is a device capable of storing one bit of binary information and retaining it until it is deliberately changed. It must have two stable states (bistability) representing logic 0 and 1, and a means of being set to either state and of having its state sensed.

Worth noting for continuity: a flip-flop is the semiconductor memory element — see 5.01 Sequential Logic Fundamentals, Latches & Flip-Flops (SR & JK) for why a flip-flop is called a one-bit memory cell. A ferrite core is the magnetic equivalent.

2. Magnetic Core Memory

Eight appearances — 2015, 2016, 2018, 2019, 2020, 2021, 2022, 2023

Question (verbatim, 2023): Define memory element. Show the information transfer process in a magnetic core memory during write and read operation. (3+7)

Earlier papers (2015, 2016, 2018, 2019, 2020) ask for the write operation only; from 2021 onward they ask for both read and write. Prepare both — the read process is where the interesting behaviour (destructive readout) lives.

2.1 The Storage Mechanism

A ferrite core is a small ring of magnetic material with a rectangular hysteresis loop — meaning it has two sharply-defined stable magnetisation states and resists anything in between.

Clockwise magnetisation $\to$ logic 1
Counter-clockwise magnetisation $\to$ logic 0

Because magnetisation persists with no power applied, core memory is non-volatile.

[GRAPH: Rectangular B-H hysteresis loop — flux density B (y-axis) vs magnetising field H (x-axis). Mark +Br and -Br (the two stable remanent states = logic 1 and 0) and ±Hc (coercivity, the field needed to flip). The near-vertical sides are what make the core act as a bistable element. Source: Mano, Digital Design — magnetic core memory section]

Terminology & Concept Breakdown

Remanence ( $B_{r}$ ): the flux density remaining after the applied field is removed — this is what stores the bit.

Coercivity ( $H_{c}$ ): the reverse field strength needed to flip the core. A field below $H_{c}$ does nothing at all; a field above it flips the core completely.

Rectangular loop: the sharp threshold at $H_{c}$ is essential — it is what makes half-current selection possible.

2.2 The Four Wires

Each core is threaded by up to four wires:

Wire	Purpose
X drive line	Carries half the switching current, $I /2$
Y drive line	Carries the other half, $I /2$
Sense line	Detects the voltage pulse induced when a core flips (used during read)
Inhibit line	Carries $- I /2$ to cancel a write where a `0` is wanted

2.3 Coincident-Current Selection — The Central Idea

This is the concept the question is really testing.

In an $n \times n$ grid, one X wire and one Y wire each carry half the current needed to flip a core:

A core on the selected X line only receives $I /2$ — below $H_{c}$ , so it does not flip.
A core on the selected Y line only receives $I /2$ — also does not flip.
The single core at the intersection receives $I /2 + I /2 = I$ — above $H_{c}$ , so it flips.

$Only the core where X and Y coincide sees the full current I \geq H_{c}$

This is why $n^{2}$ cores need only $2 n$ drive wires instead of $n^{2}$ — the economic breakthrough that made core memory practical.

graph TD
    XD["X drive line: I/2"] --> SEL["Selected core at the intersection<br/>receives I/2 + I/2 = I<br/>EXCEEDS Hc -- flips"]
    YD["Y drive line: I/2"] --> SEL
    XD --> HX["Other cores on X line<br/>receive only I/2<br/>BELOW Hc -- unchanged"]
    YD --> HY["Other cores on Y line<br/>receive only I/2<br/>BELOW Hc -- unchanged"]

2.4 The Write Operation

The address decoder energises one X line and one Y line, each with $+ I /2$ .
Only the core at their intersection experiences the full field $I > H_{c}$ and is driven clockwise = logic 1.
To write a 0 instead, the inhibit line for that bit plane carries $- I /2$ , cancelling one half-current. The core then sees only $I /2$ , stays below $H_{c}$ , and remains in its previous 0 state.
Reversing the drive-current polarity forces the core counter-clockwise, writing a 0 directly.

The inhibit wire is the detail that earns marks

Many answers describe X/Y coincidence and stop there. The follow-up question — “but how do you write a 0?” — is answered by the inhibit line subtracting $I /2$ . In a word-organised memory all bit planes are driven simultaneously, and the inhibit line is what allows individual bits within the word to differ.

2.5 The Read Operation

Drive the selected X and Y lines with current in the direction that writes a 0.
If the core held a 1, it flips from clockwise to counter-clockwise. That change of flux induces a voltage pulse on the sense wire $\to$ the bit is read as 1.
If the core already held a 0, nothing changes, no flux change occurs, and no pulse appears $\to$ the bit is read as 0.

Destructive readout — always mention this

Reading a core forces it to 0 regardless of what it contained. The stored data is destroyed by the act of reading it.

Every read must therefore be followed by a write-back (restore) cycle that rewrites the value just sensed. This is why core memory quotes a cycle time longer than its access time, and it is the single most commonly omitted point in exam answers to this question.

2.6 Answer Checklist

For the full 7–10 marks, cover:

Ferrite core with a rectangular hysteresis loop; two stable magnetisation directions = 0 and 1
The four wires: X drive, Y drive, sense, inhibit
Coincident-current selection: $I /2 + I /2 \geq H_{c}$ selects exactly one core
Write: full current sets 1; inhibit line ( $- I /2$ ) allows a 0
Read: drive to 0; flux change induces a sense-line pulse if the core held 1
Destructive readout and the required write-back cycle
Non-volatility, from remanence

3. EPROM and E²PROM

Ten appearances — 2015, 2016, 2017, 2018, 2019, 2021, 2022, 2023, 2024, 2025

Question (verbatim): Write short notes on EPROM and E²PROM. (2022 asked for EPROM alone, 5 marks.)

This is the most frequently repeated question in Chapter 7 alongside the dual-slope proof — and it is pure description, worth 5–10 marks.

3.1 EPROM — Erasable Programmable ROM

Storage mechanism: floating-gate MOSFETs. Charge trapped on an electrically isolated gate changes the transistor’s threshold voltage, which encodes the bit.
Programming: applying a high voltage (typically 12–25 V) injects hot electrons onto the floating gate.
Erasure: exposing the chip to ultraviolet light through a quartz window in the package for 20–30 minutes. UV photons give the trapped electrons enough energy to leak away.
Granularity: erasure is whole-chip only — you cannot erase a single byte.
Retention: non-volatile; data persists for years without power.
Drawback: the chip must be physically removed from the circuit and placed in a UV eraser, making field updates impractical.

3.2 E²PROM — Electrically Erasable Programmable ROM

Storage mechanism: also floating-gate, but with a much thinner tunnel oxide.
Programming and erasure: both done electrically, using voltage pulses via Fowler-Nordheim tunnelling.
Granularity: erasable and rewritable byte by byte.
In-circuit: can be reprogrammed without removing the chip — no UV source, no quartz window.
Speed: erase takes milliseconds rather than tens of minutes.
Limitation: finite endurance, typically $1 0^{4}$ – $1 0^{6}$ write/erase cycles per byte; also lower density and higher cost per bit than EPROM.

3.3 Comparison Table

Feature	EPROM	E²PROM
Erase method	Ultraviolet light through a quartz window	Electrical voltage pulses
Erase time	20–30 minutes	Milliseconds
Erase granularity	Entire chip	Byte by byte
In-circuit reprogramming	No — chip must be removed	Yes
Package	Requires transparent quartz window	Standard opaque package
Endurance	~100–1000 cycles	$1 0^{4}$ – $1 0^{6}$ cycles
Cost / density	Cheaper, denser	More expensive, less dense
Typical use	Older firmware, mask-ROM prototyping	Configuration data, calibration constants, EEPROM in microcontrollers

Structuring a "short notes" answer

For 8 marks, give roughly four points per device — storage mechanism, programming, erasure, and one limitation — then close with two or three lines of comparison. The single most important contrast is: EPROM erases optically and wholesale; E²PROM erases electrically and byte-wise, in circuit. Mentioning Flash as the modern sector-erase descendant of E²PROM is a good closing sentence.

4. Memory Classification Background

Supporting context — not directly examined

No paper from 2015 to 2025 asks for a RAM-vs-ROM or SRAM-vs-DRAM comparison. These tables are here for completeness and because they make the EPROM/E²PROM answer above easier to frame. Do not prioritise them over §2 and §3.

4.1 RAM vs ROM

Feature	RAM	ROM
Read/write	Both, freely	Read-only in normal operation
Volatility	Volatile — data lost on power-down	Non-volatile
Use	Running programs, active data	Boot firmware, fixed tables

4.2 ROM Family

Mask ROM — programmed during fabrication; cheapest at volume, unalterable.
PROM — fusible links blown once by the user.
EPROM — UV-erasable, reprogrammable (§3.1).
E²PROM — electrically erasable, byte-wise (§3.2).
Flash — E²PROM variant erasing in large sectors; the basis of SSDs and memory cards.

4.3 SRAM vs DRAM

Feature	SRAM	DRAM
Cell	6-transistor cross-coupled latch	1 transistor + 1 capacitor
Refresh	Not needed	Required every few ms
Density	Low	High
Speed	1–10 ns	30–60 ns
Use	CPU cache	Main system memory

5. Past Year Questions (PYQs)

PYQ Index for this note

Question (as asked) Years Marks Solved in
What is memory element? Show the information transfer process in a magnetic core memory during write operation 2015 (08), 2018 (08), 2020 (10) 8–10 §1, §2.4
Show the information transfer process in a magnetic core memory during write operation 2016 10 §2.4
Define memory element. Show the information transfer process during write operation 2019 10 §1, §2.4
Draw the diagram of information transfer in magnetic core memory during read and write, and explain the operating principle 2021 12 §2.3–2.5
What is memory element? Show the information transfer during read and write operation 2022 (10), 2023 (3+7) 10 §1, §2.4, §2.5
Write short notes on EPROM and E²PROM 2015 (07), 2016, 2017, 2019 (08), 2018 (08), 2021 (10), 2023, 2024, 2025 (06) 6–10 §3
Write short notes on EPROM 2022 5 §3.1

Pattern to notice: these two questions are as close to guaranteed as anything in this course — eight and ten appearances respectively. Neither needs a derivation. The magnetic core answer is a labelled diagram plus a described process; the EPROM answer is structured prose. Roughly an hour of preparation secures about 20 marks in every paper.

The trend to watch: the magnetic core question shifted from write-only (2015–2020) to read and write (2021–2023). Prepare the read process and destructive-readout point — that is where the newer marks are.

Question (as asked)	Years	Marks	Solved in
What is memory element? Show the information transfer process in a magnetic core memory during write operation	2015 (08), 2018 (08), 2020 (10)	8–10	§1, §2.4
Show the information transfer process in a magnetic core memory during write operation	2016	10	§2.4
Define memory element. Show the information transfer process during write operation	2019	10	§1, §2.4
Draw the diagram of information transfer in magnetic core memory during read and write, and explain the operating principle	2021	12	§2.3–2.5
What is memory element? Show the information transfer during read and write operation	2022 (10), 2023 (3+7)	10	§1, §2.4, §2.5
Write short notes on EPROM and E²PROM	2015 (07), 2016, 2017, 2019 (08), 2018 (08), 2021 (10), 2023, 2024, 2025 (06)	6–10	§3
Write short notes on EPROM	2022	5	§3.1

7.04 Analog-to-Digital Converters (ADC Topologies & Applications) — the other near-guaranteed Chapter 7 question (dual-slope proof)
7.03 Digital-to-Analog Converters (DAC Topologies & Analysis) — DAC comparison, seven appearances
07 Chapter Map - Multivibrators, Memory & Converters — chapter overview and exam weighting

007_index

7.02 Semiconductor & Magnetic Memory Systems

7.02 Semiconductor & Magnetic Memory Systems

1. Memory Fundamentals

2. Magnetic Core Memory

2.1 The Storage Mechanism

2.2 The Four Wires

2.3 Coincident-Current Selection — The Central Idea

2.4 The Write Operation

2.5 The Read Operation

2.6 Answer Checklist

3. EPROM and E²PROM

3.1 EPROM — Erasable Programmable ROM

3.2 E²PROM — Electrically Erasable Programmable ROM

3.3 Comparison Table

4. Memory Classification Background

4.1 RAM vs ROM

4.2 ROM Family

4.3 SRAM vs DRAM

5. Past Year Questions (PYQs)

Graph View

Table of Contents

Backlinks

007_index

7.02 Semiconductor & Magnetic Memory Systems

7.02 Semiconductor & Magnetic Memory Systems

1. Memory Fundamentals

2. Magnetic Core Memory

2.1 The Storage Mechanism

2.2 The Four Wires

2.3 Coincident-Current Selection — The Central Idea

2.4 The Write Operation

2.5 The Read Operation

2.6 Answer Checklist

3. EPROM and E²PROM

3.1 EPROM — Erasable Programmable ROM

3.2 E²PROM — Electrically Erasable Programmable ROM

3.3 Comparison Table

4. Memory Classification Background

4.1 RAM vs ROM

4.2 ROM Family

4.3 SRAM vs DRAM

5. Past Year Questions (PYQs)

6. Related Notes

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Table of Contents

Backlinks