Related Concepts: 7.02 Semiconductor & Magnetic Memory Systems | 5.01 Sequential Logic Fundamentals, Latches & Flip-Flops (SR & JK) | 07 Chapter Map - Multivibrators, Memory & Converters
7.01 Multivibrator Topologies (Astable, Monostable, Bistable & 555 Timer)
Syllabus topic with no exam history — read once, do not over-invest
No multivibrator, 555 timer, astable, monostable or bistable question appears in any ECE 2103 paper from 2015 to 2025. This was verified by full-text search of the question bank.
Earlier versions of this note carried year tags on several sections (including one marked “heavily tested”). Those tags were not supported by the question bank and have been removed.
Multivibrators are on the teaching plan (Week 8, Instructor 2), so the topic is legitimately examinable and worth one read — particularly the classification table in §1 and the 555 astable frequency formula in §4.1, which are the parts most likely to appear if it ever is asked. But it should not compete for time with the four questions that appear in almost every paper:
- Dual-slope A/D proof — 10 appearances → 7.04 Analog-to-Digital Converters (ADC Topologies & Applications)
- EPROM / E²PROM short notes — 10 appearances → 7.02 Semiconductor & Magnetic Memory Systems
- Magnetic core memory — 8 appearances → 7.02 Semiconductor & Magnetic Memory Systems
- Weighted-resistor vs R-2R DAC — 7 appearances → 7.03 Digital-to-Analog Converters (DAC Topologies & Analysis)
Overview
A Multivibrator is a regenerative electronic circuit used to implement two-state systems such as relaxation oscillators, pulse generators, timers, and flip-flops. They are categorized based on operational stability into* Bistable*,* Monostable*, and* Astable multivibrators.
1. Classification & Comparison Matrix
| Multivibrator Type | Stable States | Quasi-Stable States | Trigger Requirement | Primary Application |
|---|---|---|---|---|
| Bistable | 2 | 0 | Requires external trigger to switch states. | Flip-flops, latches, memory storage. |
| Monostable | 1 | 1 | Requires external trigger to enter quasi-stable state. | Gating circuits, delay generators, pulse shaping. |
| Astable | 0 | 2 | Self-triggering / Free-running (no trigger required). | Clock generators, square wave oscillators. |
2. BJT Transistor Astable Multivibrator
The BJT astable multivibrator consists of two cross-coupled common-emitter transistor stages (Q1, Q2) where collector outputs are AC-coupled to opposite bases via capacitors C1 and C2.
+Vcc ----+---------+---------+---------+
| | | |
[Rc1] [RB1] [RB2] [Rc2]
| | | |
+----||---+ +---||----+
| C1 | | C2 |
c1| v b2 c2| v b1
[ Q1 ] [ Q2 ] [ Q2 ] [ Q1 ]
| | | |
GND -----+---------+---------+---------+
2.1 Frequency & Period Derivation
When Q1 turns OFF, capacitor C1 charges through RB2. The base voltage vb2(t) rises exponentially toward +VCC:
vb2(t) = VCC - 2 VCC · e^(-t / (RB2 C1))
Transistor Q2 turns ON when vb2(t1) = 0 V:
0 = VCC (1 - 2 e^(-t1 / (RB2 C1))) ⇒ e^(-t1 / (RB2 C1)) = 1/2
t1 = RB2 C1 ln(2) ≈ 0.693 RB2 C1
Similarly, the second OFF-time period t2 = 0.693 RB1 C2.
Total Period (T) & Frequency (f):
If RB1 = RB2 = R and C1 = C2 = C:
T = t1 + t2 = 0.693 RC + 0.693 RC = 1.386 RC
f = 1/T = 1 / (1.386 RC) ≈ 0.72 / RC
3. IC 555 Timer Internal Architecture
The 8-pin IC 555 timer contains 2 Operational Amplifiers (Comparators), an RS Latch, a Discharge Transistor (Q1), and a 3-resistor voltage divider (5 kΩ each).
+Vcc (Pin 8)
|
[5k] -⇒ Threshold Reference (2/3 Vcc) to Comparator 1 (-)
|
[5k] -⇒ Trigger Reference (1/3 Vcc) to Comparator 2 (+)
|
[5k]
|
GND (Pin 1)
- Threshold Comparator (Comp 1): Compares Pin 6 voltage to 2/3 VCC. If VTh > 2/3 VCC, sets RS latch (R = 1).
- Trigger Comparator (Comp 2): Compares Pin 2 voltage to 1/3 VCC. If VTrig < 1/3 VCC, resets RS latch (S = 1).
4. IC 555 Timer Astable Multivibrator Mode
In astable mode, pins 2 (Trigger) and 6 (Threshold) are tied together across timing capacitor C. External resistors RA and RB control charging and discharging.
+Vcc -----+----------+
| |
[Ra] (Pin 8 - Vcc)
|
+----(Pin 7 - Discharge)
|
[Rb]
|
+----(Pin 6 - Threshold)
|
+----(Pin 2 - Trigger)
|
--- C
|
GND (Pin 1)
4.1 Timing Formulas & Duty Cycle
- Charge Time (Output HIGH, thigh): Capacitor charges from 1/3 VCC to 2/3 VCC through (RA + RB):
thigh = 0.693 (RA + RB) C
- Discharge Time (Output LOW, tlow): Capacitor discharges from 2/3 VCC to 1/3 VCC through RB:
tlow = 0.693 RB C
- Total Period (T) & Oscillation Frequency (f):
T = thigh + tlow = 0.693 (RA + 2 RB) C
f = 1/T = 1.44 / ((RA + 2 RB) C)
- Duty Cycle (D):
D = (thigh / T) = (RA + RB) / (RA + 2 RB) × 100%
Exam Trick: Achieving 50% Duty Cycle: Standard 555 astable circuits always produce D > 50% because charging path includes RA + RB while discharging path includes only RB. To achieve an exact 50% duty cycle, connect a steering diode in parallel with RB so charging bypasses RB.
5. IC 555 Timer Monostable Multivibrator Mode
In monostable mode, a negative trigger pulse at Pin 2 (< 1/3 VCC) forces the output HIGH for a single fixed time interval tW.
5.1 Pulse Width Formula Derivation
Capacitor charges from 0 V toward VCC through RA. The pulse terminates when vC(tW) = 2/3 VCC:
vC(t) = VCC (1 - e^(-t / (RA C)))
2/3 VCC = VCC (1 - e^(-tW / (RA C))) ⇒ e^(-tW / (RA C)) = 1/3
tW = RA C ln(3) ≈ 1.1 RA C
6. Past Year Master Questions & Solutions
PYQ Master Problem (2018, 2024): 555 Astable Frequency & Duty Cycle Calculation
Question: In a 555 timer astable circuit, RA = 4.7 kΩ, RB = 10 kΩ, and C = 0.1 μF. Calculate: (i) Output HIGH time thigh, (ii) Output LOW time tlow, (iii) Oscillation frequency f, (iv) Duty cycle D. [8 Marks]
Solution:
- thigh = 0.693 (4.7k + 10k) × 0.1μF = 0.693 × 14.7 × 10^3 × 10^-7 = 1.018 ms
- tlow = 0.693 (10k) × 0.1μF = 0.693 × 10^4 × 10^-7 = 0.693 ms
- T = 1.018 + 0.693 = 1.711 ms ⇒ f = 1 / 1.711 ms = 584.4 Hz
- D = 1.018 / 1.711 × 100% = 59.5%