Related Concepts: 7.03 Digital-to-Analog Converters (DAC Topologies & Analysis) | 7.02 Semiconductor & Magnetic Memory Systems | 7.01 Multivibrator Topologies (Astable, Monostable, Bistable & 555 Timer)

7.04 Analog-to-Digital Converters (ADC Topologies & Applications)

Overview

An Analog-to-Digital Converter (ADC) converts a continuous real-world analog voltage $V_{in}$ into an equivalent $N$-bit binary word $B_{N-1}\dots B_0$. Every sensor-to-processor interface — every digital voltmeter, microcontroller input and audio codec — begins with one.

The single highest-yield question in ECE 2103

The dual-slope A/D proof (§3) has appeared in ten of the eleven papers from 2015 to 2024, worth 8–13 marks each time, with near-identical wording. If you prepare one thing in this entire course, prepare that derivation.

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1. Fundamentals: Sampling & Quantization

A/D conversion happens in two stages:

1. Sampling — converting a continuous-time signal into discrete-time samples.
2. Quantization — mapping each sampled voltage onto one of a finite set of digital levels.

Terminology & Concept Breakdown

• Resolution ($V_{LSB}$): the smallest voltage change the converter can distinguish — the step size of one least-significant bit.
• Quantization error ($e_q$): the unavoidable gap between the true analog value and the nearest available digital step.
• Full-scale voltage ($V_{FS}$): the maximum input the converter can represent.

For an $N$-bit converter spanning $V_{FS}$:

$V_{LSB}=\frac{V_{FS}}{2^N}{e}_q=\pm \frac{V_{LSB}}{2}$

Quantization error is a property of the number of bits, not of the circuit quality — it can be reduced only by adding bits.

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2. Simultaneous (Flash) ADC

Not examined 2015–2025 — background only

No Flash ADC question appears in any paper. It is included for contrast, because the comparison table in §5 is genuinely useful and because Flash is the speed benchmark the other topologies are judged against. Do not spend revision time here.

A Flash ADC compares $V_{in}$ against every threshold at once using a resistor ladder and a bank of comparators feeding a priority encoder.

graph LR
    Vin["Analog Input Vin"] --> C1["Comparator 1"]
    Vin --> C2["Comparator 2"]
    Vin --> C3["Comparator 3"]
    Vref["Vref via resistor ladder"] --> C1
    Vref --> C2
    Vref --> C3
    C1 & C2 & C3 --> ENC["Priority Encoder"]
    ENC --> Out["Digital Output"]

• Comparators required: $2^N-1$ — an 8-bit Flash ADC needs $2^8-1=255$ comparators.
• Speed: one clock cycle. Nothing is faster.
• Cost: comparator count doubles per extra bit, so Flash is impractical beyond about 8 bits.

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3. Dual-Slope Integrating ADC

Ten appearances — 2015, 2016, 2017, 2018, 2019, 2020, 2021, 2022, 2023, 2024

Worth 8 to 13 marks. The wording varies only slightly: “Show that in a dual slope A/D converter, the output of the converter is proportional to the analog input voltage.” The 2022 paper says “Design…” and the 2024 paper disguises it as “For an A/D converter that is often used in digital voltmeter, prove that the output of the counter is proportional to the analog input voltage” — same question, same proof.

3.1 Circuit Architecture

graph LR
    Vin["Vin"] --> SW["Switch S"]
    Vref["-Vref"] --> SW
    SW --> INT["Integrator (R, C, op-amp)"]
    INT --> CMP["Comparator (detects zero crossing)"]
    CMP --> CTRL["Control Logic"]
    CTRL --> CNT["Binary Counter"]
    CLK["Clock f_clk"] --> CNT
    CTRL --> SW

[FIGURE: Dual-slope integrator output waveform — a triangular ramp. Fixed-slope rise over T1 whose steepness depends on Vin, then a constant-slope fall over T2 back to zero. Mark T1 (fixed) and T2 (measured). Source: Mano, Digital Design — A/D converters section]

3.2 The Proof (Mark-Bearing Derivation)

Phase 1 — Run-Up (fixed time, variable slope)

The switch connects the unknown $V_{in}$ to the integrator for a fixed interval $T_1$, set by letting the $n$-bit counter run from zero to full overflow:

$T_1=2^n{T}_{clk}$

The integrator output ramps away from zero:

$V_{peak}=-\frac{1}{RC}{\int }_0^{T_1}{V}_{in}dt=-\frac{V_{in}{T}_1}{RC}$

The steeper the ramp, the larger $V_{in}$ — the input has been converted into a voltage.

Phase 2 — Run-Down (fixed slope, variable time)

At $t=T_1$ the switch flips to a precision reference $-V_{ref}$ of opposite polarity. The integrator now ramps back toward zero at a constant rate, and the counter is restarted. The comparator stops the counter the instant the output crosses zero, after an interval $T_2=N_2{T}_{clk}$:

$\text{Change during Phase 2}=+\frac{V_{ref}{T}_2}{RC}$

Equating the two ramps

The integrator starts at zero and returns to zero, so the two areas must be equal in magnitude:

$\frac{V_{in}{T}_1}{RC}=\frac{V_{ref}{T}_2}{RC}$

$R$ and $C$ cancel immediately:

$V_{in}{T}_1=V_{ref}{T}_2$

Substituting $T_1=2^n{T}_{clk}$ and $T_2=N_2{T}_{clk}$, the clock period cancels too:

$V_{in}{2}^n{T}_{clk}=V_{ref}{N}_2{T}_{clk}$

$\boxed{{\mathbf{N}}_2=2^{\mathbf{n}}\cdot \frac{{\mathbf{V}}_{\mathbf{in}}}{{\mathbf{V}}_{\mathbf{ref}}}}$

Since $2^n$ and $V_{ref}$ are both fixed constants, the final count $N_2$ is directly proportional to $V_{in}$. $■$

The sentence that earns the last marks

“Because $R$, $C$ and $T_{clk}$ all cancel, the result is independent of component tolerance, capacitor ageing, temperature drift and clock frequency instability — which is exactly why dual-slope converters are used in precision digital voltmeters.”

This is the point of the question. The 2024 paper makes it explicit by framing the question around digital voltmeters. A derivation that stops at $N_2=2^n{V}_{in}/V_{ref}$ without stating why the cancellation matters typically loses 2–3 marks.

Where this proof goes wrong

• Forgetting that $T_1$ is fixed and $T_2$ is measured. That asymmetry is the whole mechanism — the converter turns a voltage into a time interval, and the counter measures that time.
• Writing $V_{peak}$ with the wrong sign. The integrator inverts; Phase 2 must use the opposite polarity reference or the output never returns to zero.
• Not drawing the waveform. The triangular ramp diagram with $T_1$ and $T_2$ labelled is worth marks on its own, and it makes the algebra self-evident.
• Stopping at $V_{in}{T}_1=V_{ref}{T}_2$. Push through to $N_2$ — the question asks about the output of the counter.

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4. Successive Approximation Register (SAR) ADC

A SAR ADC performs a binary search: it guesses each bit from MSB down, testing each guess with a single comparator and an internal DAC.

graph LR
    Vin["Vin"] --> CMP["Comparator"]
    DAC["Internal DAC"] --> CMP
    CMP --> SAR["SAR Control Logic"]
    SAR --> DAC
    SAR --> Out["Digital Output"]
    CLK["Clock"] --> SAR

4.1 The Algorithm

1. Set the MSB to 1, all lower bits to 0.
2. The internal DAC converts the current register contents to $V_{DAC}$.
3. Compare: if $V_{in}\ge V_{DAC}$, keep the bit as 1; if $V_{in}<V_{DAC}$, reset it to 0.
4. Move down one bit position and repeat.
5. After exactly $N$ clock cycles for $N$ bits, the register holds the result.

4.2 The Balance-and-Weights Design Problem

Major Exam Problem (PYQ 2021 — 15 marks; 2023 — 12 marks; 2025 — 09 marks)

Question (verbatim): Design a successive approximation A/D converter that can find an unknown weight in the range 0 to 1 kg using a balance and a set of weights of $\frac{1}{2}$, $\frac{1}{4}$ and $\frac{1}{8}$ kg.

This is the SAR algorithm dressed up as a physical analogy — and it is asked far more often than the abstract version.

The mapping:

SAR element	Physical equivalent
Internal DAC	The set of weights currently on the pan
Comparator	The balance beam
$V_{in}$	The unknown weight
Bit = 1	Weight stays on the pan
Bit = 0	Weight is removed
MSB → LSB order	Heaviest → lightest weight

The procedure — always start with the heaviest weight, exactly as SAR starts with the MSB:

Step	Place on pan	Balance says	Action	Bit
1	$\frac{1}{2}$ kg	unknown $\ge$ pan?	keep : remove	$b_2$
2	add $\frac{1}{4}$ kg	unknown $\ge$ pan?	keep : remove	$b_1$
3	add $\frac{1}{8}$ kg	unknown $\ge$ pan?	keep : remove	$b_0$

The result is a 3-bit word with

$\text{Weight}\approx b_2\left(\frac{1}{2}\right)+b_1\left(\frac{1}{4}\right)+b_0\left(\frac{1}{8}\right)\text{ kg},\text{resolution}=\frac{1}{8}\text{ kg}$

Worked trace — unknown weight $=0.7$ kg

Step	Pan total	Comparison	Decision	Bit
1	$0.500$	$0.7\ge 0.5$ ✓	keep $\frac{1}{2}$	$b_2=1$
2	$0.750$	$0.7<0.75$ ✗	remove $\frac{1}{4}$	$b_1=0$
3	$0.625$	$0.7\ge 0.625$ ✓	keep $\frac{1}{8}$	$b_0=1$

Result: $101_2\to 0.625$ kg. The error is $0.075$ kg, comfortably inside the $\frac{1}{8}=0.125$ kg resolution. $■$

What the examiner wants to see

Three things: (i) the explicit mapping table above showing you understand this is a SAR converter, (ii) the step-by-step procedure starting from the heaviest weight, and (iii) a worked numerical trace. Add that three weights give $2^3=8$ levels over 1 kg, hence $\frac{1}{8}$ kg resolution — that sentence answers the implicit “how good is it?” question.

4.3 The Process Question

Exam Problem (PYQ 2015, 2018 — 10 marks)

Question (verbatim): Show the successive approximation A/D conversion process with necessary diagram.

Answer with the block diagram in §4, the five-step algorithm in §4.1, and a short 3- or 4-bit worked trace. Note the fixed conversion time of exactly $N$ clock cycles regardless of input — that predictability is why SAR dominates microcontroller ADCs.

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5. ADC Architecture Comparison

Feature	Flash	Dual-Slope Integrating	Successive Approximation
Conversion time	1 clock cycle	$\approx 2^{n+1}$ clock cycles	Exactly $N$ clock cycles
Speed	Ultra-fast	Slow	Medium
Comparators	$2^N-1$	1	1
Extra hardware	Resistor ladder, priority encoder	Integrator, counter, precision $V_{ref}$	Internal DAC, SAR logic
Accuracy	Low–medium (6–8 bits)	Very high (12–20 bits)	High (10–18 bits)
Noise rejection	Poor	Excellent (averages over $T_1$)	Poor
Immune to $R$, $C$, clock drift?	No	Yes	No
Typical use	Video, oscilloscopes	Digital multimeters	Microcontroller inputs

One-line discriminator

Flash = fastest, Dual-slope = most accurate, SAR = best compromise. If asked to choose a converter for a digital voltmeter, the answer is dual-slope, and the reason is the drift cancellation proved in §3.2.

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6. Past Year Questions (PYQs)

PYQ Index for this note

Question (as asked)	Years	Marks	Solved in
Show that in a dual slope A/D converter the output of the converter is proportional to the analog input voltage	2015 (12), 2016 (11), 2017 (12), 2018 (10), 2019 (13), 2020 (10), 2021 (08), 2023 (13)	8–13	§3.2
Design a dual slope A/D converter where the output will be proportional to the analog input voltage	2022	13	§3.1, §3.2
For an A/D converter often used in digital voltmeters, prove that the output of the counter is proportional to the analog input voltage	2024	13	§3.2
Design a successive approximation A/D converter to find an unknown weight in the range 0 to 1 kg using a balance and weights of ½, ¼, ⅛ kg	2021 (15), 2023 (12), 2025 (09)	9–15	§4.2
Show the successive approximation A/D conversion process with necessary diagram	2015, 2018	10	§4.3

Pattern to notice: just two questions account for every ADC mark awarded in eleven years:

• Dual-slope proof — 10 appearances. Essentially guaranteed. The 2022 and 2024 rewordings (“design…”, “digital voltmeter…”) are the same derivation.
• SAR balance-and-weights — 3 appearances, all recent (2021, 2023, 2025), suggesting it is now a fixture.

Together they are worth roughly 20 marks per paper. Neither requires memorising a circuit from scratch — one is a four-line integral argument, the other is a three-row table.

Not examined: Flash ADC (§2) and quantization-error numericals have never appeared, despite some checklists tagging them with years. §5’s comparison table is the only reason to know Flash at all.

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7. Related Notes

• 7.03 Digital-to-Analog Converters (DAC Topologies & Analysis) — the SAR converter contains a DAC; the R-2R proof there is the DAC-side counterpart of §3.2
• 7.05 Chapter 7 Master PYQ Solutions & Converter Puzzles — additional worked converter problems
• 07 Chapter Map - Multivibrators, Memory & Converters — chapter overview and exam weighting