Related Concepts: 7.04 Analog-to-Digital Converters (ADC Topologies & Applications) | 7.02 Semiconductor & Magnetic Memory Systems | 7.01 Multivibrator Topologies (Astable, Monostable, Bistable & 555 Timer)

7.03 Digital-to-Analog Converters (DAC Topologies & Analysis)

Overview

A Digital-to-Analog Converter (DAC) transforms a binary word $B_{N-1}\dots B_0$ into a continuous analog voltage $V_o$ (or current) proportional to the digital value. It is the reverse of the ADC — and it also sits inside every successive-approximation ADC.

Two questions carry this entire note

1. Compare weighted-resistor and R-2R ladder DAC — seven appearances (2017, 2018, 2019, 2020, 2022, 2023, 2025), 7–10 marks → §4
2. Prove the R-2R output is proportional to the digital input — 2024, 2025, 9–10 marks → §3.2

Both are short. Together they are worth 15–20 marks in a typical paper.

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1. DAC Fundamentals

Resolution ($V_{LSB}$) — the analog step produced by a one-LSB change of the input:

$V_{LSB}=\frac{V_{FS}}{2^N-1}$

Analog output — the weighted sum of the input bits:

$V_o=V_{LSB}{\sum }_{i=0}^{N-1}{B}_i{2}^i$

Definitions Question (PYQ 2024, 2025 — 06 marks)

Question (verbatim, 2024): Define (i) Resolution, (ii) Accuracy, (iii) Settling time.

• Resolution — the smallest change in analog output the converter can produce, i.e. one LSB step. Often quoted as a bit count: an $N$-bit DAC resolves $2^N$ levels. $V_{LSB}=V_{FS}/(2^N-1)$.
• Accuracy — how close the actual analog output is to the ideal theoretical value, expressed as a percentage of full scale. It accounts for all error sources (offset, gain, non-linearity), so it is a system specification, not merely a step count.
• Settling time — the interval between a change of digital input and the moment the analog output settles to within $\pm \frac{1}{2}$ LSB of its final value. It sets the maximum update rate.

A fourth term worth having ready: Monotonicity — the output never decreases when the input code increases.

Resolution vs Accuracy — the distinction examiners probe

A converter can be high-resolution but inaccurate: a 16-bit DAC with a badly trimmed reference resolves tiny steps but places them all in the wrong position. Resolution is how finely you can divide the range; accuracy is how correctly. Stating this contrast explicitly is usually worth a mark on its own.

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2. Binary Weighted-Resistor DAC

An op-amp inverting summer whose input resistors are scaled in powers of two: $R,2R,4R,8R,\dots ,2^{N-1}R$.

  B3 (MSB) --->[  R  ]---+
  B2       --->[ 2R  ]---+
  B1       --->[ 4R  ]---+----(-)\
  B0 (LSB) --->[ 8R  ]---+        \____ Vo
                          +---(+)/
                          |    GND
                     [   Rf   ]
                          |
                    (feedback to Vo)

2.1 Derivation

At the inverting input the op-amp holds a virtual ground {the $-$ terminal sits at 0 V even though it is not physically connected to ground}, so each branch current depends only on its own resistor:

$I_{total}=\frac{V_{ref}}{R}{B}_3+\frac{V_{ref}}{2R}{B}_2+\frac{V_{ref}}{4R}{B}_1+\frac{V_{ref}}{8R}{B}_0$

$V_o=-I_{total}{R}_f=-V_{ref}\frac{R_f}{R}\left(B_3+\frac{B_2}{2}+\frac{B_1}{4}+\frac{B_0}{8}\right)$

The output is proportional to the digital input — but the circuit has a fatal manufacturing flaw.

The resistor-spread problem

The MSB and LSB resistors differ by a factor of $2^{N-1}$. For a 12-bit DAC that is $2^{11}=2048:1$. Fabricating resistors that hold a 2000:1 ratio to within 0.01% on one silicon die — and keeping them tracking as temperature changes — is impractical. This single sentence is the reason R-2R exists, and it is the heart of the comparison question in §4.

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3. R-2R Ladder DAC

Uses only two resistor values, $R$ and $2R$, repeated in a ladder.

   Vref
     |
   [ R ]      [ R ]      [ R ]
  ---+---------+----------+---------+
     |         |          |         |
  [ 2R ]    [ 2R ]     [ 2R ]    [ 2R ]
     |         |          |         |
    B3        B2         B1        B0        --->  Op-amp summing node ---> Vo
   (MSB)                          (LSB)

3.1 The Key Structural Property

Looking into the ladder from any node toward the LSB end, the equivalent resistance is always exactly $2R$. That self-similarity is what makes the ladder work: at every rung the available signal is split into two equal halves, so each step toward the MSB doubles a bit’s contribution.

3.2 Proof That the Output Is Proportional to the Digital Input

Major Exam Problem (PYQ 2024 — 10 marks; 2025 — 09 marks)

Question (verbatim): For an R-2R ladder D/A converter, prove that the analog output voltage is proportional to the digital input.

Step 1 — Establish the repeating $2R$ termination. The ladder is terminated at the LSB end by a $2R$ resistor to ground. At the first node, that $2R$ appears in parallel with the $2R$ branch of $B_0$:

$2R\parallel 2R=R$

Step 2 — Show the pattern repeats. That equivalent $R$ is in series with the next ladder resistor $R$, giving $2R$; which again parallels the next $2R$ branch to give $R$. The structure reproduces itself at every rung, so the resistance looking back from any node is always $2R$.

Step 3 — Apply Thévenin from LSB toward MSB. Because each node sees an identical $2R$ split, the voltage contributed by a bit is halved each time it passes one more rung toward the output. A bit $k$ rungs from the summing node therefore contributes a weight of $2^{-k}$.

Step 4 — Sum the contributions.

$\boxed{{\mathbf{V}}_{\mathbf{o}}=-{\mathbf{V}}_{\mathbf{ref}}\frac{{\mathbf{R}}_{\mathbf{f}}}{\mathbf{R}}\left(\frac{{\mathbf{B}}_{\mathbf{N}-1}}{2^1}+\frac{{\mathbf{B}}_{\mathbf{N}-2}}{2^2}+\cdots +\frac{{\mathbf{B}}_0}{2^{\mathbf{N}}}\right)}$

Every bit appears multiplied by a fixed power of two, and $V_{ref}$, $R_f$ and $R$ are constants — therefore $V_o$ is directly proportional to the digital input word. $■$

Worked numerical

For a 4-bit R-2R ladder with $V_{ref}=10\text{ V}$, $R_f=R$, and input $1011_2$: $V_o=-10\left(\frac{1}{2}+\frac{0}{4}+\frac{1}{8}+\frac{1}{16}\right)=-10(0.6875)=-6.875\text{ V}$ Sanity check: $1011_2=11$, and $\frac{11}{16}\times 10=6.875$ ✓. The magnitude is always $V_{ref}\times (\text{decimal value})/2^N$.

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4. Comparison: Weighted-Resistor vs R-2R Ladder

Seven appearances — 2017, 2018, 2019, 2020, 2022, 2023, 2025

Question (verbatim, 2018): Write down the differences between R-2R ladder and weighted register D/A converter.

(The papers print “weighted register”; they mean weighted resistor. Answer it as the weighted-resistor DAC.)

Feature	Binary Weighted-Resistor DAC	R-2R Ladder DAC
Distinct resistor values	$N$ different values: $R,2R,4R,\dots ,2^{N-1}R$	Only two: $R$ and $2R$
Resistor spread (12-bit)	$2^{11}=2048:1$	$2:1$
IC fabrication	Very difficult — wide-ratio precision resistors	Easy — repeated identical units
Temperature tracking	Poor; mismatched resistors drift differently	Excellent; identical units drift together
Accuracy at high bit counts	Degrades badly beyond ~8 bits	Maintained to 16+ bits
Circuit complexity	Simpler topology, fewer components	More resistors ($2N$), simple repeating structure
Expandability	Poor — adding a bit halves the LSB resistor tolerance budget	Good — just add another identical rung
Speed	Slightly faster (single summing node)	Marginally slower (ladder propagation)
Practical use	Teaching examples, low-resolution designs	Industry standard for monolithic DACs

The two sentences that score

“The weighted-resistor DAC needs $N$ different resistor values spanning a $2^{N-1}:1$ ratio, which cannot be fabricated accurately on an IC; the R-2R ladder achieves the same weighting with only two values, $R$ and $2R$, so all resistors can be built from identical units that track over temperature. That is why R-2R is the industry standard.”

The question is worth 7–10 marks, so give a table of 5–6 rows rather than a paragraph, and make sure the resistor-spread row is present — it is the fundamental difference from which all the others follow.

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5. Past Year Questions (PYQs)

PYQ Index for this note

Question (as asked)	Years	Marks	Solved in
Compare / write down the differences between weighted-resistor and R-2R ladder D/A converter	2017 (09), 2018, 2019, 2022, 2023 (07), 2020 (10), 2025 (08)	7–10	§4
For an R-2R ladder D/A converter, prove that the analog output voltage is proportional to the digital input	2024 (10), 2025 (09)	9–10	§3.2
Define (i) Resolution, (ii) Accuracy, (iii) Settling time	2024, 2025	6	§1
Design a 2-decade BCD D/A converter	2015	10	§6

Pattern to notice: the comparison question is the most frequent item in Chapter 7 after the dual-slope proof — seven appearances, and the wording barely changes. It requires no derivation at all, just a well-organised table. This is among the cheapest marks in the paper.

Rising item: the R-2R proof appeared for the first time in 2024 and again in 2025, alongside the definitions question in both years. Chapter 7’s DAC content is clearly being asked more heavily in recent papers, not less.

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6. BCD D/A Converter

Exam Problem (PYQ 2015 — 10 marks)

Question (verbatim): Design a 2-decade BCD D/A converter.

A 2-decade BCD DAC converts two BCD digits — the tens digit and the units digit — into one analog voltage.

• Each decade is a 4-bit BCD group driving its own 4-bit DAC section.
• The tens decade must carry ten times the weight of the units decade, so its output is scaled by a factor of 10 before summing.
• Practically: use two R-2R sections and combine them at the summing amplifier with feedback resistors in a $10:1$ ratio.

$V_o\propto 10\times (\text{tens BCD digit})+1\times (\text{units BCD digit})$

Because BCD uses only 10 of the 16 codes per nibble, a 2-decade BCD DAC spans 100 levels rather than the 256 a straight 8-bit binary DAC would provide — the trade-off being direct compatibility with decimal displays.

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7. Related Notes

• 7.04 Analog-to-Digital Converters (ADC Topologies & Applications) — the SAR ADC contains one of these DACs; the dual-slope proof there is the highest-yield question in the course
• 7.05 Chapter 7 Master PYQ Solutions & Converter Puzzles — further worked converter problems
• 07 Chapter Map - Multivibrators, Memory & Converters — chapter overview and exam weighting