7.05 Chapter 7 Master PYQ Solutions & Converter Puzzles

Related Concepts: 7.02 Semiconductor & Magnetic Memory Systems | 7.03 Digital-to-Analog Converters (DAC Topologies & Analysis) | 7.04 Analog-to-Digital Converters (ADC Topologies & Applications)

7.05 Chapter 7 Master PYQ Solutions & Converter Puzzles

OverviewDedicated problem-solving supplement for Chapter 7 (Multivibrators, Memory & Converters). Contains detailed operational schematics for Magnetic Core Memory Read/Write cycles, the SAR balance scale weight design algorithm, and the 2-decade BCD DAC architecture asked in past university exams.

1. Magnetic Core Memory Read & Write Operations [PYQ: 2015–2025]

PYQ Master Problem (2018, 2021, 2023): Magnetic Core Information TransferQuestion: Show the information transfer process in a magnetic core memory during Read and Write operations. Explain the operating principles and wire functions. [12 Marks]

1.1 Coincident-Current X-Y Matrix Architecture

A magnetic core memory array uses toroidal ferrite cores woven with four distinct wires:

1. X-Drive Wire: Carries +½ Im or -½ Im.
2. Y-Drive Wire: Carries +½ Im or -½ Im.
3. Sense Wire: Threaded through all cores in a plane to detect voltage pulses during Read.
4. Inhibit Wire: Threaded parallel to Y-wires to prevent writing 1 when writing 0.

 +X Wire (+1/2 Im)

|

+-------------v-------------+

| |

+Y Wire ------( FERRITE CORE )—⇒ +Y Wire (+1/2 Im)

(+1/2 Im) | [State = 1 or 0] |

+-------------|-------------+

v

Sense Wire / Inhibit Wire

1.2 Step-by-Step Read & Write Operations

A. Read Operation (Destructive Read Cycle)

1. Drive Currents: Apply -½ Im to the selected X-line and -½ Im to the selected Y-line.
2. Net Current: Only the target core at the X-Y intersection receives a net magnetic field H = - Im (exceeding coercivity Hc).
3. State Switching:
   1. If the core stored 1 (+Br), the net field -Im flips it to 0 (-Br). The rapid flux change induces a voltage pulse on the Sense wire.
   2. If the core stored 0 (-Br), no domain switching occurs, producing no voltage pulse on the Sense wire.
4. Destructive Read: Since reading 1 resets the core to 0, a Write/Restore cycle must immediately follow to rewrite 1 back into the core.

B. Write Operation (Restore Cycle)

1. Writing 1: Apply +½ Im to X and +½ Im to Y. Total field +Im switches core to +Br (1).
2. Writing 0: Apply +½ Im to X and +½ Im to Y, BUT simultaneously apply -½ Im to the Inhibit wire. The net current becomes +½ Im + ½ Im - ½ Im = +½ Im < Im, keeping the core in state 0.

2. SAR Balance Scale Weight Design Puzzle [PYQ: 2021, 2023, 2025]

PYQ Master Problem (2021, 2023, 2025): Successive Approximation Weight BalanceQuestion: Design a successive approximation A/D converter that can find an unknown weight WX in the range 0 to 1 kg using a balance and a set of weights of ½ kg, ¼ kg, and ⅛ kg. [12 Marks]

2.1 Algorithm & Binary Search Tree

This 3-bit SAR system represents unknown weight WX as B2 B1 B0: Wapprox = B2(½) + B1(¼) + B0(⅛)

1. Step 1 (Test MSB B2 - ½ kg): Place ½ kg on the reference pan.
   1. If Balance tilts right (WX ≥ 0.5 kg): Set B2 = 1. Keep ½ kg weight.
   2. If Balance tilts left (WX < 0.5 kg): Set B2 = 0. Remove ½ kg weight.
2. Step 2 (Test Bit B1 - ¼ kg): Add ¼ kg weight to reference pan.
   1. If Total Reference Weight ≤ WX: Set B1 = 1. Keep ¼ kg weight.
   2. If Total Reference Weight > WX: Set B1 = 0. Remove ¼ kg weight.
3. Step 3 (Test LSB B0 - ⅛ kg): Add ⅛ kg weight to reference pan.
   1. If Total Reference Weight ≤ WX: Set B0 = 1. Keep ⅛ kg weight.
   2. If Total Reference Weight > WX: Set B0 = 0. Remove ⅛ kg weight.

Example Decision Execution (WX = 0.65 kg)

Step	Added Weight	Total Tested Weight	Balance Status (WX ≥ Wtested?)	Bit Result	Kept Weights
1	½ = 0.500 kg	0.500 kg	Yes (0.65 ≥ 0.500)	B2 = 1	½ kg
2	¼ = 0.250 kg	0.750 kg	No (0.65 < 0.750)	B1 = 0	½ kg
3	⅛ = 0.125 kg	0.625 kg	Yes (0.65 ≥ 0.625)	B0 = 1	½ + ⅛ kg

Final Digital Output Code: B2 B1 B0 = 1012 (5 × ⅛ = 0.625 kg).

3. 2-Decade BCD D/A Converter Design [PYQ: 2015]

PYQ Master Problem (2015): 2-Decade BCD DACQuestion: Design a 2-decade BCD D/A converter using weighted resistors. [10 Marks]

3.1 Circuit Design & Weighting Equation

A 2-decade BCD DAC processes two decimal digits (Tens decade T3 T2 T1 T0 and Units decade U3 U2 U1 U0).

 Tens Inputs (T3, T2, T1, T0) -⇒[ Resistors R, 2R, 4R, 8R ]----\

[ OP-AMP SUMMING ]-⇒ V_o

Units Inputs (U3, U2, U1, U0) -⇒[ Resistors 10R, 20R, 40R, 80R ]/

Output Equation

Vo = - Vref (Rf/R) ([ T3 + T2/2 + T1/4 + T0/8 ] + 1/10 [ U3 + U2/2 + U1/4 + U0/8 ])