07 Chapter Map - Multivibrators, Memory & Converters
Chapter 7 Overview & Map of Content (MOC)
Multivibrator circuit topologies (BJT astable/monostable, 555 timer astable/monostable), semiconductor memory (RAM, ROM, SRAM, DRAM), magnetic storage systems, Digital-to-Analog Converters (weighted-resistor, R-2R ladder), and Analog-to-Digital Converters (Flash, Dual-Slope, SAR ADC).
📚 Study Notes Index
- 7.01 Multivibrator Topologies (Astable, Monostable, Bistable & 555 Timer)
- 7.02 Semiconductor & Magnetic Memory Systems
- 7.03 Digital-to-Analog Converters (DAC Topologies & Analysis)
- 7.04 Analog-to-Digital Converters (ADC Topologies & Applications)
- 7.05 Chapter 7 Master PYQ Solutions & Converter Puzzles
🔗 Related Resources
- Course Teaching Plan: ECE 2103 - Digital Electronics and Logic Circuits
- Instructor: Foysal Sir (Instructor 2)
7.01 Multivibrator Topologies (Astable, Monostable, Bistable & 555 Timer)
Overview: A Multivibrator is a regenerative electronic circuit used to implement two-state systems such as relaxation oscillators, pulse generators, timers, and flip-flops. They are categorized based on operational stability into Bistable*,* Monostable*, and* Astable multivibrators.
1. Classification & Comparison Matrix
| Multivibrator Type | Stable States | Quasi-Stable States | Trigger Requirement | Primary Application |
|---|---|---|---|---|
| Bistable | 2 | 0 | Requires external trigger to switch states. | Flip-flops, latches, memory storage. |
| Monostable | 1 | 1 | Requires external trigger to enter quasi-stable state. | Gating circuits, delay generators, pulse shaping. |
| Astable | 0 | 2 | Self-triggering / Free-running (no trigger required). | Clock generators, square wave oscillators. |
2. BJT Transistor Astable Multivibrator [PYQ: 2015, 2017, 2021]
The BJT astable multivibrator consists of two cross-coupled common-emitter transistor stages (Q1, Q2) where collector outputs are AC-coupled to opposite bases via capacitors C1 and C2.
+Vcc ----+---------+---------+---------+
| | | |
[Rc1] [RB1] [RB2] [Rc2]
| | | |
+----||---+ +---||----+
| C1 | | C2 |
c1| v b2 c2| v b1
[ Q1 ] [ Q2 ] [ Q2 ] [ Q1 ]
| | | |
GND -----+---------+---------+---------+
2.1 Frequency & Period Derivation [PYQ: 2015, 2017, 2021]
When Q1 turns OFF, capacitor C1 charges through RB2. The base voltage vb2(t) rises exponentially toward +VCC:
vb2(t) = VCC - 2 VCC · e^(-t / (RB2 C1))
Transistor Q2 turns ON when vb2(t1) = 0 V:
0 = VCC (1 - 2 e^(-t1 / (RB2 C1))) ⇒ e^(-t1 / (RB2 C1)) = 1/2
t1 = RB2 C1 ln(2) ≈ 0.693 RB2 C1
Similarly, the second OFF-time period t2 = 0.693 RB1 C2.
Total Period (T) & Frequency (f):
If RB1 = RB2 = R and C1 = C2 = C:
T = t1 + t2 = 0.693 RC + 0.693 RC = 1.386 RC
f = 1/T = 1 / (1.386 RC) ≈ 0.72 / RC
3. IC 555 Timer Internal Architecture [PYQ: 2016, 2019, 2022]
The 8-pin IC 555 timer contains 2 Operational Amplifiers (Comparators), an RS Latch, a Discharge Transistor (Q1), and a 3-resistor voltage divider (5 kΩ each).
+Vcc (Pin 8)
|
[5k] -⇒ Threshold Reference (2/3 Vcc) to Comparator 1 (-)
|
[5k] -⇒ Trigger Reference (1/3 Vcc) to Comparator 2 (+)
|
[5k]
|
GND (Pin 1)
- Threshold Comparator (Comp 1): Compares Pin 6 voltage to 2/3 VCC. If VTh > 2/3 VCC, sets RS latch (R = 1).
- Trigger Comparator (Comp 2): Compares Pin 2 voltage to 1/3 VCC. If VTrig < 1/3 VCC, resets RS latch (S = 1).
4. IC 555 Timer Astable Multivibrator Mode [PYQ: Heavily Tested: 2015, 2018, 2020, 2024]
In astable mode, pins 2 (Trigger) and 6 (Threshold) are tied together across timing capacitor C. External resistors RA and RB control charging and discharging.
+Vcc -----+----------+
| |
[Ra] (Pin 8 - Vcc)
|
+----(Pin 7 - Discharge)
|
[Rb]
|
+----(Pin 6 - Threshold)
|
+----(Pin 2 - Trigger)
|
--- C
|
GND (Pin 1)
4.1 Timing Formulas & Duty Cycle [PYQ: 2015, 2018, 2020, 2024]
- Charge Time (Output HIGH, thigh): Capacitor charges from 1/3 VCC to 2/3 VCC through (RA + RB):
thigh = 0.693 (RA + RB) C
- Discharge Time (Output LOW, tlow): Capacitor discharges from 2/3 VCC to 1/3 VCC through RB:
tlow = 0.693 RB C
- Total Period (T) & Oscillation Frequency (f):
T = thigh + tlow = 0.693 (RA + 2 RB) C
f = 1/T = 1.44 / ((RA + 2 RB) C)
- Duty Cycle (D):
D = (thigh / T) = (RA + RB) / (RA + 2 RB) × 100%
Exam Trick: Achieving 50% Duty Cycle: Standard 555 astable circuits always produce D > 50% because charging path includes RA + RB while discharging path includes only RB. To achieve an exact 50% duty cycle, connect a steering diode in parallel with RB so charging bypasses RB.
5. IC 555 Timer Monostable Multivibrator Mode [PYQ: 2017, 2023]
In monostable mode, a negative trigger pulse at Pin 2 (< 1/3 VCC) forces the output HIGH for a single fixed time interval tW.
5.1 Pulse Width Formula Derivation [PYQ: 2017, 2023]
Capacitor charges from 0 V toward VCC through RA. The pulse terminates when vC(tW) = 2/3 VCC:
vC(t) = VCC (1 - e^(-t / (RA C)))
2/3 VCC = VCC (1 - e^(-tW / (RA C))) ⇒ e^(-tW / (RA C)) = 1/3
tW = RA C ln(3) ≈ 1.1 RA C
6. Past Year Master Questions & Solutions
PYQ Master Problem (2018, 2024): 555 Astable Frequency & Duty Cycle Calculation
Question: In a 555 timer astable circuit, RA = 4.7 kΩ, RB = 10 kΩ, and C = 0.1 μF. Calculate: (i) Output HIGH time thigh, (ii) Output LOW time tlow, (iii) Oscillation frequency f, (iv) Duty cycle D. [8 Marks]
Solution:
- thigh = 0.693 (4.7k + 10k) × 0.1μF = 0.693 × 14.7 × 10^3 × 10^-7 = 1.018 ms
- tlow = 0.693 (10k) × 0.1μF = 0.693 × 10^4 × 10^-7 = 0.693 ms
- T = 1.018 + 0.693 = 1.711 ms ⇒ f = 1 / 1.711 ms = 584.4 Hz
- D = 1.018 / 1.711 × 100% = 59.5%
7.02 Semiconductor & Magnetic Memory Systems
Related Concepts: 7.01 Multivibrator Topologies (Astable, Monostable, Bistable & 555 Timer) | 7.03 Digital-to-Analog Converters (DAC Topologies & Analysis) | 6.01 Registers, Parallel Load & Shift Register Dynamics
Overview: Semiconductor and magnetic memory systems store binary information in modern computing architectures. They are organized into arrays of Memory Cells characterized by access speed, storage density, power consumption, and volatility.
1. Fundamentals of Memory Organization & Capacity [PYQ: 2016, 2019, 2022]
- Memory Cell: The basic 1-bit bistable storage element.
- Memory Word: A group of M bits stored and retrieved together as a single unit at a specific address (e.g., 8-bit byte, 32-bit word).
- Address Lines (K): K binary address lines can uniquely select 2^K memory locations.
- Data Lines (M): M bidirectional lines transfer data into or out of the selected memory word.
1.1 Memory Capacity Calculation Formula [PYQ: 2016, 2019]
Total Capacity (Bits) = 2^K × M
Total Capacity (Bytes) = (2^K × M) / 8
Example: A memory chip has 12 address lines (K=12) and 8 data lines (M=8). Total Words = 2^12 = 4096 = 4 K words. Total Capacity = 4096 × 8 bits = 32,768 bits = 4 KB.
2. RAM vs. ROM Classification Matrix [PYQ: Heavily Tested: 2015–2025]
| Feature | RAM (Random Access Memory) | ROM (Read-Only Memory) |
|---|---|---|
| Read/Write Capability | Read and Write operations performed easily. | Read-only during normal operation. |
| Volatility | Volatile (data lost when power is turned off). | Non-Volatile (data retained indefinitely without power). |
| Primary Use Case | Main system memory (executing programs & active variables). | Boot firmware (BIOS, bootloader, microcode). |
| Operation Speed | Very fast (nanosecond access times). | Fast read, extremely slow/complex write or program cycle. |
3. ROM Technologies & Variants [PYQ: 2017, 2020, 2024]
- MROM (Mask ROM): Programmed permanently during IC fabrication using photo-masks. Inexpensive in huge quantities; cannot be altered.
- PROM (Programmable ROM): Blank chip containing fusible links burned once by the user using a high-voltage PROM programmer.
- EPROM (Erasable PROM): Uses floating-gate MOSFETs. Erased completely by exposing the quartz window to Ultraviolet (UV) light for 20-30 minutes.
- EEPROM (Electrically EPROM): Erased and reprogrammed byte-by-byte in-circuit using electrical voltage pulses.
- Flash Memory: Non-volatile EEPROM variant that erased data in large sector blocks, offering high density and high speed (used in SSDs, SD cards).
4. SRAM vs. DRAM Architecture [PYQ: 2018, 2021, 2023]
Semiconductor RAM is divided into Static RAM (SRAM) and Dynamic RAM (DRAM):
SRAM Cell (6T MOSFET Latch) DRAM Cell (1T1C Structure)
+---------------+ Bit Line
| Cross-Coupled | |
BL —⇒| Inverters (4T)|⇐— BL’ [ FET ]
| + 2T Select | |
+---------------+ --- Capacitor (C)
| GND
4.1 Quantitative Comparison Table
| Feature | Static RAM (SRAM) | Dynamic RAM (DRAM) [PYQ: 2018, 2021, 2023] |
|---|---|---|
| Storage Element | Cross-coupled flip-flop latch (6 MOSFETs per cell). | Single storage capacitor + 1 pass transistor (1T1C per cell). |
| Refresh Requirement | No refresh required as long as power is maintained. | Periodic refresh required every few milliseconds due to capacitor leakage. |
| Packing Density | Low (large 6T cell area). | High (compact 1T1C cell area, enabling gigabyte density). |
| Speed & Latency | Extremely Fast (1-10 ns). | Slower (30-60 ns due to charge/discharge overhead). |
| Cost & Power | Expensive, high power consumption. | Cheap per bit, low static power. |
| Application | CPU Cache memory (L1, L2, L3 cache). | System Main Memory (DDR4, DDR5 RAM). |
5. Magnetic Memory Systems [PYQ: 2016, 2018, 2021]
Magnetic memory stores binary data using the orientation of magnetic dipoles in ferromagnetic materials.
5.1 Magnetic Core Memory
- Mechanism: Small ferrite rings (cores) threaded with write wires (X, Y) and sense wires. Magnetization direction (clockwise vs. counter-clockwise) represents binary 1 or 0.
5.2 Hard Disk Drives (HDD) & Magnetic Hysteresis Loop
- Platters & Heads: Spinning platters coated with iron oxide or cobalt alloy. An inductive read-write head magnetizes micro-domains on circular concentric tracks.
- B-H Hysteresis Principle:
- Remanence (Br): The residual magnetic flux density remaining after the external magnetic field H is removed. This guarantees non-volatility.
- Coercivity (Hc): The reverse magnetic field strength required to reduce magnetization to zero (determines write stability).
Magnetization B
^
| * Saturation
| /
+Br | * (Residual Remanence = Binary 1)
-----|—+-----------------⇒ Field H
-Hc | |
| | -Br (Residual Remanence = Binary 0)
7.03 Digital-to-Analog Converters (DAC Topologies & Analysis)
Related Concepts: 7.01 Multivibrator Topologies (Astable, Monostable, Bistable & 555 Timer) | 7.04 Analog-to-Digital Converters (ADC Topologies & Applications) | 7.02 Semiconductor & Magnetic Memory Systems
7.03 Digital-to-Analog Converters (DAC Topologies & Analysis)
Overview: A Digital-to-Analog Converter (DAC) transforms discrete binary digital words (B_N … B_1) into a continuous analog voltage (V_o) or current (I_o) proportional to the digital value.
1. DAC Fundamentals & Resolution Math
- Resolution (V_LSB): The smallest incremental analog output change corresponding to a 1-bit LSB change:
V_LSB = Step Size = V_FS / (2^N - 1)
Where V_FS is Full-Scale Voltage and N is the bit resolution.
- 2. Analog Output Formula:
V_o = V_LSB * (Σ B_i 2^i) = [V_FS / (2^N - 1)] * (B_{N-1} 2^{N-1} + … + B_1 2^1 + B_0 2^0)
2. Binary Weighted-Resistor DAC [PYQ: 2016, 2019, 2022]
Uses an Op-Amp inverting summing configuration with input resistors weighted in powers of two (R, 2R, 4R, 8R, …, 2^{N-1}R).
B3 (MSB) -⇒[ R ]----+
B2 -------⇒[ 2R ]---+
B1 -------⇒[ 4R ]---+-⇒ (-)
B0 (LSB) -⇒[ 8R ]---+ | [ Op-Amp ]---⇒ V_o
+→ (+) GND
|
+---[ Rf ]---+
|
V_o
2.1 Mathematical Derivation [PYQ: 2016, 2019, 2022]
Applying KCL at the inverting virtual ground node (V_- = 0 V):
I_total = I_3 + I_2 + I_1 + I_0 = (V_ref/R)B_3 + (V_ref/2R)B_2 + (V_ref/4R)B_1 + (V_ref/8R)B_0
V_o = - I_total Rf = - V_ref (Rf/R) * (B_3 + B_2/2 + B_1/4 + B_0/8)
Major Drawback of Weighted-Resistor DAC: For a 12-bit DAC, the ratio between the MSB and LSB resistor is 2^{12-1} = 2048. Manufacturing resistors with precise tolerances across a 2000:1 ratio on a single silicon IC is extremely difficult and temperature-unstable.
3. R-2R Ladder DAC (Industry Standard) [PYQ: Heavily Tested: 2015, 2017, 2020, 2023, 2025]
The R-2R Ladder DAC overcomes resistor ratio limitations by using strictly two resistor values: R and 2R.
Vref —+ Node 3 Node 2 Node 1 Node 0
| | | | |
| [ 2R ] [ 2R ] [ 2R ] [ 2R ]
| | | | |
| v v v v
| (B3) (B2) (B1) (B0)
| | | | |
+—[ R ]---+----[ R ]----+----[ R ]----+----[ 2R ]---+
|
v
Op-Amp Inverting Summing Node -⇒ V_o
3.1 Thevenin Equivalent Derivation Proof [PYQ: 2015, 2017, 2020, 2023, 2025]
Mathematical Proof: Looking back into any node k of the R-2R ladder toward the LSB, the equivalent resistance looking in any direction is always exactly 2R. By applying Thevenin’s theorem repeatedly from LSB to MSB, each binary bit contributes a voltage weight that is halved at each subsequent node step.
V_o = - V_ref (Rf/R) * (B_{N-1}/2^1 + B_{N-2}/2^2 + … + B_0/2^N)
Advantage over Weighted-Resistor DAC: Requires only two precision resistor values (R and 2R), making it ideal for monolithic IC fabrication with superior temperature tracking.
4. Key DAC Performance Specifications [PYQ: 2018, 2021, 2024]
- Monotonicity: A DAC is monotonic if the analog output always increases or stays constant as the digital input increases.
- Settling Time: Time taken for output to settle within ± 1/2 LSB of its final value after input change.
- Linearity Error (INL & DNL): Integral and Differential Non-Linearity measuring deviations from an ideal straight-line transfer curve.
5. Past Year Master Questions & Solutions
PYQ Master Problem (2020, 2023, 2025): 4-Bit R-2R Ladder Analysis
Question: Draw the circuit diagram of a 4-bit R-2R ladder DAC. Derive the output voltage equation using node analysis. Calculate V_o if V_ref = 10 V, Rf = R, and input is 1011_2. [10 Marks]
Solution:
-
-
- Draw R-2R schematic (Section 3).
-
- Apply formula for 1011_2: V_o = - 10 V * (1/2 + 0/4 + 1/8 + 1/16) = - 10 * (0.5 + 0 + 0.125 + 0.0625) = -6.875 V
-
7.04 Analog-to-Digital Converters (ADC Topologies & Applications)
Related Concepts: 7.03 Digital-to-Analog Converters (DAC Topologies & Analysis) | 7.01 Multivibrator Topologies (Astable, Monostable, Bistable & 555 Timer) | 7.02 Semiconductor & Magnetic Memory Systems
Overview: An Analog-to-Digital Converter (ADC) converts a continuous real-world analog voltage (Vin) into an equivalent N-bit binary digital word (BN-1 … B0).
1. Fundamentals & Quantization Error [PYQ: 2019, 2022]
A/D conversion involves two distinct steps:
- Sampling: Converting a continuous-time signal into discrete time samples.
- Quantization: Approximating continuous voltage levels into discrete digital steps.
Quantization Error (eq) [PYQ: 2019, 2022]: Because an ADC maps an infinite continuous voltage range into 2N discrete steps, there is an inherent mathematical uncertainty called Quantization Error (eq), bounded by:
eq = ± VLSB / 2 = ± VFS / [2 (2N - 1)]
2. Simultaneous / Flash ADC (Fastest Topology) [PYQ: 2015, 2018, 2021, 2024]
Flash ADCs compare the input voltage Vin simultaneously against 2N - 1 reference thresholds using a resistor divider ladder and parallel op-amp comparators.
Vref ----[ R/2 ]----+----(-) Comp 3
|
Vin ----------------+----(+) Comp 3 —⇒ [ PRIORITY ]
| [ ENCODER ]---⇒ Digital
[ R ] -----+----(-) Comp 2 —⇒ [ ] Output (B1, B0)
| [ ]
Vin ----------------+----(+) Comp 2
|
[ R ] -----+----(-) Comp 1 —⇒ [ ]
|
Vin ----------------+----(+) Comp 1
2.1 Hardware Complexity & Trade-Offs
- Number of Comparators Required: For N bits, exactly 2N - 1 comparators are required (e.g., an 8-bit Flash ADC requires 28 - 1 = 255 comparators).
- Conversion Speed: Ultra-fast (conversion occurs in a single clock pulse tc = 1 cycle).
- Limitation: High power consumption, large die area, and high cost for resolutions > 8 bits.
3. Dual-Slope Integrating ADC (Most Accurate Topology) [PYQ: 2016, 2020, 2023]
Dual-slope ADCs convert voltage into a time interval using an integrator and a precision clock counter.
Vin ---\
[ SW 1 ]-⇒[ INTEGRATOR ]-⇒[ COMPARATOR ]-⇒[ COUNTER CONTROL ]
-Vref -/
3.1 Operational Phases & Mathematical Proof [PYQ: 2016, 2020, 2023]
- Phase 1 (Run-Up Phase): Switch connects Vin to integrator for a fixed clock count N1 = 2n (T1 = 2n × Tclk). Output voltage reaches: Vpeak = - (1/RC) Vin T1
- Phase 2 (Run-Down Phase): Switch connects reference voltage -Vref until integrator returns to 0 V (T2 = N2 × Tclk): Vpeak = (1/RC) Vref T2
- Equating Output Voltages: (1/RC) Vin T1 = (1/RC) Vref T2 implies Vin N1 = Vref N2. Thus, N2 = (Vin / Vref) 2n
Major Advantage of Dual-Slope ADC: The final count N2 is completely independent of R, C, and clock frequency fclk*. Component aging, temperature drift, and clock frequency instability cancel out completely, providing exceptional measurement precision.*
4. Successive Approximation Register (SAR) ADC [PYQ: 2017, 2019, 2022, 2025]
SAR ADCs employ a binary search algorithm using an internal DAC, a single comparator, and control logic.
Vin -⇒(+) [ COMPARATOR ]
(-) ^
|
[ DAC ] ⇐- [ SAR LOGIC REGISTER ] ⇐- System CLK
4.1 Binary Search Algorithm
- Clear SAR register to 1000…02 (MSB set to ‘1’).
- Internal DAC converts SAR register content to analog VDAC.
- Comparator compares Vin against VDAC: If Vin ≥ VDAC: Keep MSB as ‘1’; If Vin < VDAC: Reset MSB to ‘0’.
- Move to the next bit position and repeat testing.
- Fixed Conversion Time: Requires exactly N clock cycles for an N-bit conversion.
5. Master ADC Architecture Comparison Matrix [PYQ: 2015–2025]
| Feature | Flash ADC | Dual-Slope Integrating ADC | Successive Approximation (SAR) |
|---|---|---|---|
| Conversion Speed | Ultra-Fast (1 clock cycle). | Slow (2n+1 clock cycles). | Medium (N clock cycles). |
| Circuit Complexity | Very High (2N - 1 comparators). | Medium (Integrator + Counter). | Low (1 Comparator + 1 DAC). |
| Accuracy | Low to Medium (6-8 bits). | Extremely High (12-20 bits). | High (10-18 bits). |
| Primary Application | Video, Oscilloscopes. | Digital Multimeters (DMMs). | Microcontroller ADCs. |
6. Past Year Master Questions & Solutions
PYQ Master Problem (2018, 2021, 2024): Flash ADC Comparator Calculation
Question: An 8-bit Flash ADC has VFS = 10.24 V. Determine: (i) Comparators required, (ii) Resolution VLSB, (iii) Max quantization error eq.
Solution:
- Comparators: 28 - 1 = 255
- VLSB: 10.24 / 255 ≈ 40.15 mV
- eq: ± VLSB / 2 = ± 20.08 mV
7.05 Chapter 7 Master PYQ Solutions & Converter Puzzles
Related Concepts: 7.02 Semiconductor & Magnetic Memory Systems | 7.03 Digital-to-Analog Converters (DAC Topologies & Analysis) | 7.04 Analog-to-Digital Converters (ADC Topologies & Applications)
7.05 Chapter 7 Master PYQ Solutions & Converter Puzzles
OverviewDedicated problem-solving supplement for Chapter 7 (Multivibrators, Memory & Converters). Contains detailed operational schematics for Magnetic Core Memory Read/Write cycles, the SAR balance scale weight design algorithm, and the 2-decade BCD DAC architecture asked in past university exams.
1. Magnetic Core Memory Read & Write Operations [PYQ: 2015–2025]
PYQ Master Problem (2018, 2021, 2023): Magnetic Core Information TransferQuestion: Show the information transfer process in a magnetic core memory during Read and Write operations. Explain the operating principles and wire functions. [12 Marks]
1.1 Coincident-Current X-Y Matrix Architecture
A magnetic core memory array uses toroidal ferrite cores woven with four distinct wires:
- X-Drive Wire: Carries +½ Im or -½ Im.
- Y-Drive Wire: Carries +½ Im or -½ Im.
- Sense Wire: Threaded through all cores in a plane to detect voltage pulses during Read.
- Inhibit Wire: Threaded parallel to Y-wires to prevent writing 1 when writing 0.
+X Wire (+1/2 Im)
|
+-------------v-------------+
| |
+Y Wire ------( FERRITE CORE )—⇒ +Y Wire (+1/2 Im)
(+1/2 Im) | [State = 1 or 0] |
+-------------|-------------+
v
Sense Wire / Inhibit Wire
1.2 Step-by-Step Read & Write Operations
A. Read Operation (Destructive Read Cycle)
- Drive Currents: Apply -½ Im to the selected X-line and -½ Im to the selected Y-line.
- Net Current: Only the target core at the X-Y intersection receives a net magnetic field H = - Im (exceeding coercivity Hc).
- State Switching:
- If the core stored 1 (+Br), the net field -Im flips it to 0 (-Br). The rapid flux change induces a voltage pulse on the Sense wire.
- If the core stored 0 (-Br), no domain switching occurs, producing no voltage pulse on the Sense wire.
- Destructive Read: Since reading 1 resets the core to 0, a Write/Restore cycle must immediately follow to rewrite 1 back into the core.
B. Write Operation (Restore Cycle)
- Writing 1: Apply +½ Im to X and +½ Im to Y. Total field +Im switches core to +Br (1).
- Writing 0: Apply +½ Im to X and +½ Im to Y, BUT simultaneously apply -½ Im to the Inhibit wire. The net current becomes +½ Im + ½ Im - ½ Im = +½ Im < Im, keeping the core in state 0.
2. SAR Balance Scale Weight Design Puzzle [PYQ: 2021, 2023, 2025]
PYQ Master Problem (2021, 2023, 2025): Successive Approximation Weight BalanceQuestion: Design a successive approximation A/D converter that can find an unknown weight WX in the range 0 to 1 kg using a balance and a set of weights of ½ kg, ¼ kg, and ⅛ kg. [12 Marks]
2.1 Algorithm & Binary Search Tree
This 3-bit SAR system represents unknown weight WX as B2 B1 B0: Wapprox = B2(½) + B1(¼) + B0(⅛)
- Step 1 (Test MSB B2 - ½ kg): Place ½ kg on the reference pan.
- If Balance tilts right (WX ≥ 0.5 kg): Set B2 = 1. Keep ½ kg weight.
- If Balance tilts left (WX < 0.5 kg): Set B2 = 0. Remove ½ kg weight.
- Step 2 (Test Bit B1 - ¼ kg): Add ¼ kg weight to reference pan.
- If Total Reference Weight ≤ WX: Set B1 = 1. Keep ¼ kg weight.
- If Total Reference Weight > WX: Set B1 = 0. Remove ¼ kg weight.
- Step 3 (Test LSB B0 - ⅛ kg): Add ⅛ kg weight to reference pan.
- If Total Reference Weight ≤ WX: Set B0 = 1. Keep ⅛ kg weight.
- If Total Reference Weight > WX: Set B0 = 0. Remove ⅛ kg weight.
Example Decision Execution (WX = 0.65 kg)
| Step | Added Weight | Total Tested Weight | Balance Status (WX ≥ Wtested?) | Bit Result | Kept Weights |
|---|---|---|---|---|---|
| 1 | ½ = 0.500 kg | 0.500 kg | Yes (0.65 ≥ 0.500) | B2 = 1 | ½ kg |
| 2 | ¼ = 0.250 kg | 0.750 kg | No (0.65 < 0.750) | B1 = 0 | ½ kg |
| 3 | ⅛ = 0.125 kg | 0.625 kg | Yes (0.65 ≥ 0.625) | B0 = 1 | ½ + ⅛ kg |
Final Digital Output Code: B2 B1 B0 = 1012 (5 × ⅛ = 0.625 kg).
3. 2-Decade BCD D/A Converter Design [PYQ: 2015]
PYQ Master Problem (2015): 2-Decade BCD DACQuestion: Design a 2-decade BCD D/A converter using weighted resistors. [10 Marks]
3.1 Circuit Design & Weighting Equation
A 2-decade BCD DAC processes two decimal digits (Tens decade T3 T2 T1 T0 and Units decade U3 U2 U1 U0).
Tens Inputs (T3, T2, T1, T0) -⇒[ Resistors R, 2R, 4R, 8R ]----\
[ OP-AMP SUMMING ]-⇒ V_o
Units Inputs (U3, U2, U1, U0) -⇒[ Resistors 10R, 20R, 40R, 80R ]/
Output Equation
Vo = - Vref (Rf/R) ([ T3 + T2/2 + T1/4 + T0/8 ] + 1/10 [ U3 + U2/2 + U1/4 + U0/8 ])
7.06 Semiconductor & Magnetic Memory Core Operations
In-depth analysis of semiconductor memory cell electronics (6T SRAM latches, 1T1C DRAM refresh dynamics, Flash floating gates) and magnetic core coincident-current selection (X-Y matrix, destructive read-out, restore cycle).
1. Semiconductor Memory Hierarchy & Comparison Matrix
| Memory Type | Cell Structure | Volatility | Refresh Needed | Relative Speed | Density |
|---|---|---|---|---|---|
| SRAM | Cross-coupled 6T MOSFET latch | Volatile | No | Extremely Fast (1-10 ns) | Low |
| DRAM | 1T MOSFET + 1 Storage Capacitor (1T1C) | Volatile | Yes (2-64 ms) | Fast (30-60 ns) | High |
| EPROM | Floating-Gate MOSFET (UV erased) | Non-Volatile | No | Fast Read / Slow Write | Medium |
| EEPROM | Floating-Gate MOSFET (Electrically erased) | Non-Volatile | No | Fast Read / Slow Write | Medium |
| Flash | Block-erasable Floating-Gate array | Non-Volatile | No | Fast Read / Block Write | High |
2. Magnetic Core Memory Read & Write Operations [PYQ: 2015–2025]
A magnetic core memory array uses toroidal ferrite cores woven with four distinct wires:
- X-Drive Wire: Carries +1/2Im or -1/2Im.
- Y-Drive Wire: Carries +1/2Im or -1/2Im.
- Sense Wire: Threaded through all cores in a plane to detect voltage pulses during Read.
- Inhibit Wire: Threaded parallel to Y-wires to prevent writing 1 when writing 0.
2.1 Operational Cycles
- Destructive Read: Apply -1/2Im to selected X and Y wires. Net field -Im flips core from 1 (+Br) to 0 (-Br), inducing a voltage pulse on the Sense wire.
- Write / Restore Cycle: Apply +1/2Im to X and Y. To write 0, apply -1/2Im to the Inhibit wire to cancel net field to +1/2Im < Im.
7.07 Multivibrator Waveforms, 555 Timer & Timing Derivations
aliases:
- BJT Astable Frequency Derivation
- BJT Monostable Pulse Width
- 555 Timer Architecture
- 555 Astable & Monostable Timing Equations
- 50% Duty Cycle Extension
tags:
- digital-electronics
- ece-2103
- term-2-1
- study-order/7.07
type: uni-note
course: “ECE 2103 - Digital Electronics and Logic Circuits”
chapter_map: “07 Chapter Map - Multivibrators, Memory & Converters”
term: 2-1
teacher: Foysal Sir
status: enhanced
Related Concepts: 7.01 Multivibrator Topologies (Astable, Monostable, Bistable & 555 Timer) | 7.03 Digital-to-Analog Converters (DAC Topologies & Analysis) | 7.02 Semiconductor & Magnetic Memory Systems
7.07 Multivibrator Waveforms, 555 Timer & Timing Derivations
Overview: Complete mathematical derivations for BJT astable/monostable relaxation oscillators and IC 555 timer configurations.
1. BJT Astable Multivibrator Frequency Derivation [PYQ: 2015, 2017, 2021]
Base voltage vb2(t) rises exponentially during charging:
vb2(t) = VCC - 2 VCC e^-t / (RB C)
Setting vb2(t1) = 0 V:
t1 = RB C ln(2) ≈ 0.693 RB C
Total Period T = t1 + t2 = 1.386 RB C ⇒ f = 1 / (1.386 RB C) ≈ 0.72 / (RB C)
2. IC 555 Timer Astable Mode [PYQ: 2015, 2018, 2020, 2024]
- thigh = 0.693 (RA + RB) C
- tlow = 0.693 RB C
- f = 1.44 / ((RA + 2RB) C)
- Duty Cycle D = (RA + RB) / (RA + 2RB) x 100%
50% Duty Cycle Steering Diode
Connect a diode in parallel with RB (anode to Pin 7, cathode to Pin 6). Charging bypasses RB directly through RA, yielding thigh = 0.693 RA C. Setting RA = RB gives D = 50%.
7.08 Digital-to-Analog Converters (DAC Topologies & Proofs)
Related Concepts: 7.03 Digital-to-Analog Converters (DAC Topologies & Analysis) | 7.04 Analog-to-Digital Converters (ADC Topologies & Applications) | 7.09 Analog-to-Digital Converters (ADC Topologies & SAR Search)
7.08 Digital-to-Analog Converters (DAC Topologies & Proofs)
Overview: Nodal analysis proofs for Weighted-Resistor and R-2R ladder DACs, performance metrics (INL, DNL, settling time), and 2-decade BCD DAC design.
1. Weighted-Resistor vs R-2R Ladder DAC Matrix
| Metric | Weighted-Resistor DAC | R-2R Ladder DAC |
|---|---|---|
| Resistor Values | N different values (R, 2R, 4R, …, 2^{N-1}R). | Strictly two values (R and 2R). |
| Resistor Ratio Spread | 2^{N-1}:1 (High spread, e.g. 2048:1 for 12-bit). | 2:1 ratio (Low spread, easy IC tracking). |
| Monolithic IC Suitability | Poor due to resistance spread. | Excellent. |
2. R-2R Ladder Nodal Proof [PYQ: 2015, 2017, 2020, 2023, 2025]
Output voltage formula for N-bit input B_{N-1} … B_0:
V_o = - V_{ref} (R_f / R) * [ (B_{N-1} / 2^1) + (B_{N-2} / 2^2) + … + (B_0 / 2^N) ]
7.09 Analog-to-Digital Converters (ADC Topologies & SAR Search)
Overview: Comparative analysis of Flash, Dual-Slope, and SAR ADCs, including integration calculus proofs and the balance-scale binary search algorithm.
1. Master ADC Topologies Matrix
| Topology | Speed | Conversion Time | Comparators Required | Noise Rejection |
|---|---|---|---|---|
| Flash ADC | Ultra-Fast (>100 MSPS) | 1 clock cycle | 2^N - 1 | Poor |
| Dual-Slope ADC | Slow (<100 SPS) | 2^{n+1} clock cycles | 1 | Exceptional |
| SAR ADC | Medium (1-5 MSPS) | N clock cycles | 1 | Moderate |
2. Dual-Slope Proportionality Proof [PYQ: 2016, 2020, 2023]
Equating run-up peak voltage V_peak = (V_in * T_1) / RC to run-down time T_2 (V_peak = (V_ref * T_2) / RC):
V_in * T_1 = V_ref * T_2 ⇒ N_2 = (V_in / V_ref) * 2
The digital count N_2 is independent of R, C, and clock frequency.
3. SAR Balance Scale Weight Search Algorithm [PYQ: 2021, 2023, 2025]
To measure unknown weight W_X (0 to 1 kg) using weights 1/2, 1/4, 1/8 kg:
- Step 1 (B_2): Place 1/2 kg. If W_X >= 0.5, keep weight (B_2=1); else remove (B_2=0).
- Step 2 (B_1): Add 1/4 kg. If W_X >= W_tested, keep weight (B_1=1); else remove (B_1=0).
- Step 3 (B_0): Add 1/8 kg. If W_X >= W_tested, keep weight (B_0=1); else remove (B_0=0).
00 Chapter 7 Active-Recall Diagnostic Quiz (Multivibrators, Memory & Converters)
Overview: Test your conceptual understanding and exam readiness for multivibrators, 555 timers, RAM/ROM architectures, magnetic memory, DAC topologies, and ADC techniques.
Question 1: Multivibrator Stability States
How many stable and quasi-stable states exist in an Astable vs. Monostable vs. Bistable multivibrator?
Solution:
- Astable: 0 stable states, 2 quasi-stable states (free-running oscillator).
- Monostable: 1 stable state, 1 quasi-stable state (single pulse generator).
- Bistable: 2 stable states, 0 quasi-stable states (flip-flop memory cell).
Question 2: 555 Astable Frequency Formula
Write the frequency formula f for a 555 timer connected in astable mode with resistors R_A, R_B and capacitor C.
Solution:
f = 1.44 / ((R_A + 2 R_B) C)
Question 3: 555 Timer Duty Cycle Extension
Why does a standard 555 astable circuit always produce a duty cycle D > 50%, and how can an exact 50% duty cycle be achieved?
Solution:
Charging occurs through R_A + R_B, while discharging occurs only through R_B, making t_high > t_low (D = (R_A+R_B)/(R_A+2R_B) > 50%). To achieve D=50%, connect a steering diode in parallel with R_B so charging bypasses R_B directly through R_A.
Question 4: SRAM vs. DRAM Refresh Requirement
Why does DRAM require periodic electrical refresh cycles while SRAM does not?
Solution:
- DRAM: Stores charge on a tiny 1T1C MOS capacitor that leaks charge over time (2-64 ms), requiring periodic refresh cycles to restore charge.
- SRAM: Stores data in a cross-coupled 6-transistor (6T) flip-flop latch that holds state indefinitely as long as power is applied.
Question 5: EPROM vs. EEPROM Erasure
How is stored data erased in an EPROM vs. an EEPROM chip?
Solution:
- EPROM: Erased entirely by exposing the chip’s quartz window to Ultraviolet (UV) light for 20-30 minutes.
- EEPROM: Erased byte-by-byte or in sectors in-circuit using electrical voltage pulses.
Question 6: Magnetic Core Destructive Read
Why is a Read operation in magnetic core memory termed a “Destructive Read”?
Solution:
Reading is performed by applying drive currents that force the core to state 0. If the core stored a 1, the flux change induces a voltage pulse on the sense wire, but the state 1 is destroyed (reset to 0). A write/restore cycle must immediately follow to rewrite 1 back into the core.
Question 7: R-2R Ladder DAC Advantage
What is the primary manufacturing advantage of an R-2R Ladder DAC over a Binary Weighted-Resistor DAC?
Solution:
The weighted-resistor DAC requires N precision resistor values spanning a 2^(N-1):1 ratio, which is difficult to fabricate on an IC. The R-2R ladder requires only two resistor values (R and 2R), providing superior temperature tracking and ease of monolithic IC fabrication.
Question 8: ADC Quantization Error Bounds
What is the maximum quantization error e_q for an N-bit ADC with full-scale voltage V_FS?
Solution:
e_q = +/- V_LSB / 2 = +/- V_FS / (2(2^N - 1))
Question 9: Dual-Slope ADC Independence Proof
Why is the digital output count N_2 of a Dual-Slope Integrating ADC independent of component tolerances (R, C) and clock frequency?
Solution:
Integrator peak voltage during run-up is V_peak = (V_in * T_1) / (R * C). Run-down time T_2 to return to 0 V is V_peak = (V_ref * T_2) / (R * C). Equating both gives V_in * T_1 = V_ref * T_2 ⇒ N_2 = (V_in / V_ref) * 2^n. The terms R, C, and clock period T_clk cancel out completely!
Question 10: Flash ADC Hardware Explosion
How many parallel voltage comparators are required to construct an 8-bit Flash ADC?
Solution:
Comparators = 2^N - 1 = 2^8 - 1 = 256 - 1 = 255 comparators