7.09 Analog-to-Digital Converters (ADC Topologies & SAR Search)
Overview: Comparative analysis of Flash, Dual-Slope, and SAR ADCs, including integration calculus proofs and the balance-scale binary search algorithm.
1. Master ADC Topologies Matrix
| Topology | Speed | Conversion Time | Comparators Required | Noise Rejection |
|---|---|---|---|---|
| Flash ADC | Ultra-Fast (>100 MSPS) | 1 clock cycle | 2^N - 1 | Poor |
| Dual-Slope ADC | Slow (<100 SPS) | 2^{n+1} clock cycles | 1 | Exceptional |
| SAR ADC | Medium (1-5 MSPS) | N clock cycles | 1 | Moderate |
2. Dual-Slope Proportionality Proof [PYQ: 2016, 2020, 2023]
Equating run-up peak voltage V_peak = (V_in * T_1) / RC to run-down time T_2 (V_peak = (V_ref * T_2) / RC):
V_in * T_1 = V_ref * T_2 ⇒ N_2 = (V_in / V_ref) * 2
The digital count N_2 is independent of R, C, and clock frequency.
3. SAR Balance Scale Weight Search Algorithm [PYQ: 2021, 2023, 2025]
To measure unknown weight W_X (0 to 1 kg) using weights 1/2, 1/4, 1/8 kg:
- Step 1 (B_2): Place 1/2 kg. If W_X >= 0.5, keep weight (B_2=1); else remove (B_2=0).
- Step 2 (B_1): Add 1/4 kg. If W_X >= W_tested, keep weight (B_1=1); else remove (B_1=0).
- Step 3 (B_0): Add 1/8 kg. If W_X >= W_tested, keep weight (B_0=1); else remove (B_0=0).