05 Chapter Map - Combinational Circuit Design
Chapter 5 Overview & Map of Content (MOC)
Arithmetic circuits (HAs, FAs, multipliers, comparators), Code converters, MUX/Decoder/DeMUX tree networks, PLDs (ROM & PLA), application word problems, and edge-case logic synthesis.
📚 Study Notes Index
| # | Note | What it covers | PYQ years | Typical marks |
|---|---|---|---|---|
| 5.01 | 5.01 Arithmetic Circuits, Multipliers & Comparators | Design blueprint, three-half-adder puzzle, FA→FS conversion, carry look-ahead | 2015, 2018, 2019, 2020 | 10–12 |
| 5.02 | 5.02 Code Converters & Data Routing Implementations | 2421→84-2-1 converter, MUX and decoder implementations, Shannon expansion | 2016–2025 (most papers) | 8–13 |
| 5.03 | 5.03 Tree Networks (Cascading MUX, Decoders & DeMUX) | 16-to-1 MUX tree, 4-to-16 and 5×32 decoders, 1×16 demux | 2016, 2017, 2021, 2023, 2024, 2025 | 8–12 |
| 5.04 | 5.04 Programmable Logic Devices (ROM & PLA) | ROM square generator, PLA with shared product terms, ROM vs PLA | 2015, 2017, 2018, 2020, 2021, 2023, 2024, 2025 | 5–13 |
| 5.05 | 5.05 Application-Specific Word Problems | Restaurant, spaceship, boiler, divisibility | 2016, 2017, 2021, 2022 | 8–13 |
| 5.06 | 5.06 Combinational Hardware Edge Cases & Logic Synthesis | 4-to-1 MUX from NAND, decoder with unsimplified functions | 2016, 2017, 2018, 2020 | 10–12 |
🎯 Exam Weight
The heaviest-scoring chapter in the paper
Chapter 5 reliably supplies 30–40 marks, almost all of it design work. Ranked by frequency:
Rank Question Appearances Marks Note 1 2,4,2,1 → 8,4,-2,-1 code converter 6 8–13 5.02 Code Converters & Data Routing Implementations §2 2 ROM 3-bit square generator 5 8–13 5.04 Programmable Logic Devices (ROM & PLA) §1 3 MUX function implementation 5 10 5.02 Code Converters & Data Routing Implementations §3.3 4 PLA with four product terms 4 10–12 5.04 Programmable Logic Devices (ROM & PLA) §2 5 Decoder tree networks 4 8–12 5.03 Tree Networks (Cascading MUX, Decoders & DeMUX) 6 Decoder with 3 10–12 5.02 Code Converters & Data Routing Implementations §5.1 7 Three half-adders () 3 10–12 5.01 Arithmetic Circuits, Multipliers & Comparators §2 The top four use the same functions and the same numbers every year. Working each once properly is worth more than any amount of general revision.
The unifying insight for this whole chapter
Decoders, multiplexers, ROMs and PLAs all exist to let you skip Boolean simplification:
- Decoder — hands you every minterm on a pin; just OR the ones you need
- MUX — fold one variable into the data inputs; read , , or off pairs of rows
- ROM — plug the truth table straight in; no minimisation at all
- PLA — the only one that does need simplification, and it needs it on all four forms () to find shared terms
When a question names one of these devices, reach for the truth table, not the K-map.
Sections in this chapter that have never been examined
The 2-bit multiplier, magnitude comparator and BCD adder (all in 5.01 Arithmetic Circuits, Multipliers & Comparators), and the BCD to seven-segment decoder (5.02 Code Converters & Data Routing Implementations §6) do not appear in any theory paper from 2015 to 2025. Some checklists tag them with years; those tags do not survive a check against the question bank. The seven-segment decoder is ECE 2104 Lab Week 9, so learn it for the lab.
🔗 Related Resources
- Course Teaching Plan: ECE 2103 - Digital Electronics and Logic Circuits
- Previous chapter: 04 Chapter Map - Universal Gates & Advanced Logic Families — the gate-level hardware these MSI blocks are built from
- Prerequisite: 03 Chapter Map - Boolean Algebra & Logic Simplification — K-maps and don’t cares, used throughout the converter and word-problem designs
- Lab tie-in (ECE 2104): Week 3 half/full adders and subtractors; Week 4 BCD→Excess-3; Week 5 Gray↔Binary; Week 9 BCD→seven-segment.