Related Concepts: 02 Code Converters & Data Routing Implementations | 03 Tree Networks (Cascading MUX, Decoders & DeMUX) | 04 Programmable Logic Devices (ROM & PLA)

5.06 Combinational Hardware Edge Cases & Logic Synthesis

Hardware Restrictions & Synthesis

Advanced exam questions test your ability to synthesize functions into restricted hardware architectures {such as designing a MUX using ONLY NAND gates or expanding unsimplified equations for a Decoder}.

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1. Design a 4-to-1 MUX using ONLY NAND Gates

Major PYQ Problem (2018 - 10 Marks)

Question: Design a 4-to-1 line multiplexer using NAND gates.

Solution:

1. MUX SOP Equation: $Y=S_1^{\prime }{S}_0^{\prime }{I}_0+S_1^{\prime }{S}_0{I}_1+S_1{S}_0^{\prime }{I}_2+S_1{S}_0{I}_3$
2. NAND-NAND Transformation: $Y=\overline{\overline{S_1^{\prime }{S}_0^{\prime }{I}_0}\cdot \overline{S_1^{\prime }{S}_0{I}_1}\cdot \overline{S_1{S}_0^{\prime }{I}_2}\cdot \overline{S_1{S}_0{I}_3}}$
3. Circuit Construction:
   • Two 2-input NAND gates (inputs tied) to produce $S_1^{\prime }$ and $S_0^{\prime }$.
   • Four 3-input NAND gates in Level 1.
   • One 4-input NAND gate in Level 2. $■$

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2. Multi-Equation Decoder Implementation

Major PYQ Problem (2016, 2017, 2019, 2020 - 12 Marks)

Question: Design a circuit using a 3-to-8 decoder and external OR gates for:

• $F_1=x^{\prime }{y}^{\prime }+xy{z}^{\prime }$
• $F_2=x^{\prime }+y$
• $F_3=xy+x^{\prime }{y}^{\prime }$

Canonical Minterm Expansion Solution:

1. Expand $F_1$: $x^{\prime }{y}^{\prime }(z+z^{\prime })+xy{z}^{\prime }=x^{\prime }{y}^{\prime }z+x^{\prime }{y}^{\prime }{z}^{\prime }+xy{z}^{\prime }⟹{\mathbf{F}}_1=\sum \mathbf{m}(0,1,6)$

2. Expand $F_2$: $x^{\prime }(y+y^{\prime })(z+z^{\prime })+y(x+x^{\prime })(z+z^{\prime })⟹{\mathbf{F}}_2=\sum \mathbf{m}(0,1,2,3,6,7)$

3. Expand $F_3$: $xy(z+z^{\prime })+x^{\prime }{y}^{\prime }(z+z^{\prime })⟹{\mathbf{F}}_3=\sum \mathbf{m}(0,1,6,7)$

Circuit Implementation:

• Connect inputs $x,y,z$ to a 3-to-8 decoder.
• $F_1$: Wire decoder pins 0, 1, 6 into a 3-input OR gate.
• $F_2$: Wire decoder pins 0, 1, 2, 3, 6, 7 into a 6-input OR gate (or pins 4, 5 into a 2-input NOR gate).
• $F_3$: Wire decoder pins 0, 1, 6, 7 into a 4-input OR gate. $■$

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Past Year Questions (PYQs)

• [PYQ 2018]: 4-to-1 MUX using ONLY NAND gates. (10 Marks)
• [PYQ 2016, 2017, 2019, 2020]: Multi-equation decoder implementation with unsimplified expressions. (12 Marks)