Related Concepts: 4.01 Digital Systems & Signal Propagation | 4.02 Universal Logic Gates & 2-Level Implementations | 3.01 Boolean Algebra Foundations & Duality Principle

4.07 Logic Analysis, Switching Circuits & Positive-Negative Logic

Advanced Physical Logic Concepts

Analyzing physical digital circuits requires converting hardware voltage states or physical mechanical switches into formal Boolean algebraic notation.

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1. Positive & Negative Logic Systems

In hardware, binary values (1 and 0) are assigned to voltage levels ($V_H$ and $V_L$):

• Positive Logic System: High Voltage $V_H=1$, Low Voltage $V_L=0$.
• Negative Logic System: High Voltage $V_H=0$, Low Voltage $V_L=1$.

Major Exam Proof (PYQ 2015, 2018, 2019, 2023, 2025 — 7 to 12 marks)

Question (verbatim, 2019): Show that a positive-logic AND gate is a negative-logic OR gate and vice-versa.

In 2015 and 2018 this was part (ii) of a two-part question whose part (i) was the XOR duality proof — see 3.01 Boolean Algebra Foundations & Duality Principle §2. Revise the pair together.

Proof Solution:

Step 1: Physical Voltage Truth Table

Consider a hardware gate that outputs High voltage ($H$) ONLY when both inputs are High ($H$):

Input X	Input Y	Output Z
$L$	$L$	$L$
$L$	$H$	$L$
$H$	$L$	$L$
$H$	$H$	$H$

Step 2: Positive Logic Assignment ($H=1,L=0$)

Substituting $H=1,L=0$: $\text{Table: }(0,0\to 0),(0,1\to 0),(1,0\to 0),(1,1\to 1)⟹\mathbf{Z}=\mathbf{X}\cdot \mathbf{Y}(\text{AND Gate})$

Step 3: Negative Logic Assignment ($H=0,L=1$)

Substituting $H=0,L=1$: $\text{Table: }(1,1\to 1),(1,0\to 1),(0,1\to 1),(0,0\to 0)⟹\mathbf{Z}=\mathbf{X}+\mathbf{Y}(\text{OR Gate})$

$\therefore \text{Positive-Logic AND Gate}\equiv \text{Negative-Logic OR Gate}■$

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2. Physical Switching Circuit Translation Rules

Major Exam Switch Puzzle (PYQ 2024 — 07 marks; 2025 — 08 marks)

Question (verbatim, 2025): Express the following switching circuit shown in Figure 1(c) in a binary logic notation (Light in ‘ON’ condition).

The phrase “light in ON condition” tells you what the output variable means: write the Boolean expression for the condition under which current reaches the lamp.

graph TD
    Switch[Physical Mechanical Switches] --> Series[Series Connection: Switch A and B end-to-end]
    Switch --> Parallel[Parallel Connection: Switch A and B side-by-side]
    Switch --> NC[Normally-Closed Contact]
    
    Series --> AND[Boolean AND Logic: A • B]
    Parallel --> OR[Boolean OR Logic: A + B]
    NC --> NOT[Boolean Inversion: A']

Golden Rules:

1. Series Switches: Forms AND ($\cdot$) logic. Current flows if both switches are closed.
2. Parallel Switches: Forms OR ($+$) logic. Current flows if either switch is closed.
3. Normally-Closed Contact: Forms NOT (${}^{\prime }$) logic. Opening switch breaks circuit.

How to read a switching diagram without panicking

Trace every distinct path from the supply to the lamp:

• Each complete path is one product term — AND together every switch lying along it.
• The full expression is the OR of all such paths, because the lamp lights if any path conducts.
• A switch drawn with a bar over its label, or described as normally-closed, contributes a complemented literal.

Worked shape: if switch $A$ sits in series with a parallel block of $B$ and $C$, and that whole branch parallels a lone switch $D$, then $\text{Light}=A(B+C)+D$.

Finish the job: these questions usually award marks for simplifying the expression and sketching the equivalent gate network too — the 2016 paper asks for this explicitly. Do not stop at the raw expression.

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3. Formal Multi-Level Intermediate Variable Analysis (Morris Mano Method)

Multi-Level Analysis Algorithm (2016, 2019 - 12 Marks)

1. Label Level 1 Outputs: Assign intermediate variable symbols ($T_1,T_2$) to outputs of gates driven purely by primary inputs.
2. Label Level 2 Outputs: Assign symbols ($T_3,T_4$) to subsequent level gate outputs driven by $T_1,T_2$.
3. Sequential Substitution: Express $T_3=f(T_1,T_2)$, then substitute original input variables ($A,B,C$) backwards to derive output $F$.

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4. PYQ Master Methodology: Circuit Analysis to Single Gate

PYQ Note: Circuit Analysis to a Single Gate (PYQ 2023 — 08 marks)

Question (verbatim): Represent the logic circuit in Fig. 2(c) with only a single logic gate.

When a question hands you a drawn circuit and asks for the expression, a simplification, or a single-gate equivalent:

1. Assign intermediate variables ($T_1,T_2,\dots$) to the outputs of the first level of gates.
2. Cascade forward until you have the unsimplified output expression.
3. Simplify algebraically or with a K-map.

When the question says “a single logic gate”, the target is almost always XOR or XNOR — those are the only two-input functions that look complicated in gate form but collapse to one symbol. So watch for the shapes $A^{\prime }B+A{B}^{\prime }$ (XOR) and $AB+A^{\prime }{B}^{\prime }$ (XNOR) as you simplify. Note this is a strong hint, not a guarantee: in 2018, 2019, 2020 and 2022 the same figures were asked only to be simplified or rebuilt in NAND, and those answers were ordinary SOP expressions.

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Past Year Questions (PYQs)

Question (as asked)	Years	Marks	Solved in
Show that a positive-logic AND gate is a negative-logic OR gate and vice-versa	2015, 2018, 2019, 2023, 2025	7–12	§1
Define positive and negative logic system (inside a multi-part definitions question)	2015, 2016	part of 10	§1
Express the switching circuit of Fig. 1(b) / 1(c) in binary logic notation	2024, 2025	7–8	§2
Find a simplified switching expression and logic network for the circuit of Fig. 2(b)	2016	12	§2, §3
Simplify the logic circuit of Fig. 2(c) and construct the simplified circuit using only NAND gates	2018	10	§3, and 4.02 Universal Logic Gates & 2-Level Implementations
Simplify the logic circuit shown in Fig. 2(b)	2019	12	§3
Determine the Boolean function for the output $F$ of the circuit shown in Fig. 2(c)	2020	10	§3
Simplify the logic circuit shown in Fig. 2(c)	2022	8	§3
Represent the logic circuit in Fig. 2(c) with only a single logic gate	2023	8	§4

Pattern to notice: “here is a drawn circuit — analyse it” appears in six consecutive papers (2016, 2018, 2019, 2020, 2022, 2023), worth 8–12 marks every time. It is effectively guaranteed. Only the closing instruction changes:

• “determine the Boolean function” → stop at the simplified expression
• “simplify” → simplify and redraw
• “using only NAND gates” → convert via bubble-pushing
• “a single logic gate” → drive it to XOR/XNOR

Read the final clause before you start, and make sure your answer actually ends where the question asks it to.

The positive/negative logic proof is equally reliable — five appearances. It needs no algebra at all: one voltage-level truth table, then relabel it twice. Roughly ten minutes to learn, 7–12 marks every time it appears.