Related Concepts: 01 Digital Systems & Signal Propagation | 02 Universal Logic Gates & 2-Level Implementations | 06 CMOS Logic & Logic Gate Characteristics

4.07 Logic Analysis, Switching Circuits & Positive-Negative Logic

Advanced Physical Logic Concepts

Analyzing physical digital circuits requires converting hardware voltage states or physical mechanical switches into formal Boolean algebraic notation.

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1. Positive & Negative Logic Systems

In hardware, binary values (1 and 0) are assigned to voltage levels ($V_H$ and $V_L$):

• Positive Logic System: High Voltage $V_H=1$, Low Voltage $V_L=0$.
• Negative Logic System: High Voltage $V_H=0$, Low Voltage $V_L=1$.

Major Exam Proof: Positive AND = Negative OR (2015, 2019, 2023, 2025 - 11 Marks)

Question: Prove mathematically that a Positive-Logic AND gate is a Negative-Logic OR gate and vice-versa.

Proof Solution:

Step 1: Physical Voltage Truth Table

Consider a hardware gate that outputs High voltage ($H$) ONLY when both inputs are High ($H$):

Input X	Input Y	Output Z
$L$	$L$	$L$
$L$	$H$	$L$
$H$	$L$	$L$
$H$	$H$	$H$

Step 2: Positive Logic Assignment ($H=1,L=0$)

Substituting $H=1,L=0$: $\text{Table: }(0,0\to 0),(0,1\to 0),(1,0\to 0),(1,1\to 1)⟹\mathbf{Z}=\mathbf{X}\cdot \mathbf{Y}(\text{AND Gate})$

Step 3: Negative Logic Assignment ($H=0,L=1$)

Substituting $H=0,L=1$: $\text{Table: }(1,1\to 1),(1,0\to 1),(0,1\to 1),(0,0\to 0)⟹\mathbf{Z}=\mathbf{X}+\mathbf{Y}(\text{OR Gate})$

$\therefore \text{Positive-Logic AND Gate}\equiv \text{Negative-Logic OR Gate}■$

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2. Physical Switching Circuit Translation Rules

Major Exam Switch Puzzle (2024, 2025 - 7 Marks)

graph TD
    Switch[Physical Mechanical Switches] --> Series[Series Connection: Switch A and B end-to-end]
    Switch --> Parallel[Parallel Connection: Switch A and B side-by-side]
    Switch --> NC[Normally-Closed Contact]
    
    Series --> AND[Boolean AND Logic: A • B]
    Parallel --> OR[Boolean OR Logic: A + B]
    NC --> NOT[Boolean Inversion: A']

Golden Rules:

1. Series Switches: Forms AND ($\cdot$) logic. Current flows if both switches are closed.
2. Parallel Switches: Forms OR ($+$) logic. Current flows if either switch is closed.
3. Normally-Closed Contact: Forms NOT (${}^{\prime }$) logic. Opening switch breaks circuit.

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3. Formal Multi-Level Intermediate Variable Analysis (Morris Mano Method)

Multi-Level Analysis Algorithm (2016, 2019 - 12 Marks)

1. Label Level 1 Outputs: Assign intermediate variable symbols ($T_1,T_2$) to outputs of gates driven purely by primary inputs.
2. Label Level 2 Outputs: Assign symbols ($T_3,T_4$) to subsequent level gate outputs driven by $T_1,T_2$.
3. Sequential Substitution: Express $T_3=f(T_1,T_2)$, then substitute original input variables ($A,B,C$) backwards to derive output $F$.

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4. PYQ Master Methodology: Circuit Analysis to Single Gate

PYQ Note (2023): Circuit Analysis to Single Gate

When an exam question provides a drawn logic circuit (e.g. Fig 2c in 2023) and asks to “extract the Boolean expression and reduce to a single logic gate”:

1. Assign intermediate variables ($T_1,T_2$) to the outputs of the first level of gates.
2. Cascade the equations forward until you derive the unsimplified output expression.
3. Apply Boolean algebra simplification. The resulting algebraic expression will always factor down into either an XOR ($A\oplus B=A^{\prime }B+A{B}^{\prime }$) or an XNOR ($A\odot B=AB+A^{\prime }{B}^{\prime }$) expression, allowing implementation via a single gate! $■$

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Past Year Questions (PYQs)

• [PYQ 2015, 2019, 2023, 2025]: Positive-logic AND = Negative-logic OR proof. (11 Marks)
• [PYQ 2024, 2025]: Express switching circuit diagram into binary logic expression. (07 Marks)
• [PYQ 2016, 2019]: Multi-level logic circuit analysis using intermediate variables. (12 Marks)
• [PYQ 2023]: Analyze drawn circuit diagram and reduce to a single logic gate. (08 Marks)