04 Chapter Map - Universal Gates & Advanced Logic Families
Chapter 4 Overview & Map of Content (MOC)
Universal gate implementations (NAND/NOR), 2-level logic synthesis, transistor switches, DTL, Totem-Pole TTL, Open Collector bus systems, CMOS NAND, ECL/I2L overviews, and switching circuit analysis.
📚 Study Notes Index
| # | Note | What it covers | PYQ years | Typical marks |
|---|---|---|---|---|
| 4.01 | 4.01 Digital Systems & Signal Propagation | Digital vs analog, signal degradation, regeneration | — | — |
| 4.02 | 4.02 Universal Logic Gates & 2-Level Implementations | NAND/NOR universality, two-level forms, degenerate forms, bubble-pushing, gate-limited NOR designs | 2015, 2018, 2021, 2022, 2024 | 7–11 |
| 4.03 | 4.03 BJT as NOT Gate & Inverter Operation | Cut-off/saturation switching, the inverter proof | 2016, 2019 | 13 |
| 4.04 | 4.04 Diode Logic & DTL Logic Families | Diode AND/OR, npn characteristic curves, DTL saturation proof | 2021, 2022 | 9–10 |
| 4.05 | 4.05 TTL Logic Families & Open Collector Bus Systems | TTL NAND and AND circuits, totem-pole conflict, open collector, wired-AND, common bus | 2015, 2019, 2023, 2025 | 7–11 |
| 4.06 | 4.06 CMOS Logic & Logic Gate Characteristics | CMOS NAND/NOR, ECL, the five characteristic definitions, family comparison | 2016, 2018, 2019, 2021, 2023, 2024, 2025 | 5–10 |
| 4.07 | 4.07 Logic Analysis, Switching Circuits & Positive-Negative Logic | Positive/negative logic proof, switching circuits, drawn-circuit analysis | 2015–2025 (most papers) | 7–12 |
🎯 Exam Weight
Chapter 4 carries the two most repeated questions in the course
- The characteristics definitions — fan-out, propagation delay, noise margin, power dissipation, current sourcing. Seven appearances (2016, 2018, 2019, 2021, 2023, 2024, 2025), 6–10 marks, pure recall → 4.06 CMOS Logic & Logic Gate Characteristics §4
- Drawn-circuit analysis — “here is Fig. 2(b)/2(c), analyse it”. Six consecutive papers (2016, 2018, 2019, 2020, 2022, 2023), 8–12 marks → 4.07 Logic Analysis, Switching Circuits & Positive-Negative Logic §3
Next tier, all highly reliable:
- Positive-logic AND = negative-logic OR — five appearances, no algebra required
- BJT inverter proof — 2016, 2019, identical parameters, 13 marks each
- DTL saturation proof — 2021, 2022, same method as the inverter proof
- NOR implementation with a gate limit — 2015, 2021, 2024
Two procedures cover four papers each
- The saturation test () solves both the BJT inverter (4.03) and the DTL proof (4.04) — 2016, 2019, 2021, 2022.
- Group the zeros, build with complemented inputs solves every NOR-implementation question (4.02) — 2015, 2021, 2024.
Gate-identity traps in this chapter
- TTL AND vs TTL NAND — 2023 asked AND, 2025 asked NAND. They differ by one inverting stage.
- NOR vs NAND implementation — group the
0s for NOR, the1s for NAND.- “Power distribution” in the 2016, 2018 and 2021 papers means power dissipation.
Syllabus topics never examined
Diode AND/OR gates, ECL circuit analysis, and IIL/I²L have not appeared in any paper 2015–2025, despite being listed in Weeks 7–8. Read them once for context; do not build revision sessions around them.
🔗 Related Resources
- Course Teaching Plan: ECE 2103 - Digital Electronics and Logic Circuits
- Previous chapter: 03 Chapter Map - Boolean Algebra & Logic Simplification — the minimisation that feeds these hardware implementations
- Next chapter: 05 Chapter Map - Combinational Circuit Design — building adders, converters, MUXes and PLAs from these gates
- Lab tie-in (ECE 2104): Weeks 1–2 cover gate IC testing and universal gate verification.