Related Concepts: 03 Logic Gate Characteristics & Buffer Gates | 04 NPN Transistor Basics & DTL Logic | 05 TTL Logic Families & Open Collector Bus Systems

4.06 CMOS Logic & Logic Gate Characteristics

Concept Overview: CMOS & Specialized Bipolar Families

CMOS (Complementary Metal-Oxide Semiconductor) uses complementary pairs of p-channel (PMOS) and n-channel (NMOS) MOSFETs. It is the dominant VLSI logic family due to its near-zero static power consumption and extremely high integration density.

graph TD
    subgraph CMOS 3-Input NAND Network Architecture
        VDD[Power Supply VDD] --> PUN[Pull-Up Network: 3 PMOS Transistors in PARALLEL]
        PUN --> OutY[Output Node Y]
        OutY --> PDN[Pull-Down Network: 3 NMOS Transistors in SERIES]
        PDN --> GND[Ground VSS]
    end

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1. 3-Input CMOS NAND Gate Operation

Major PYQ Problem: 3-Input CMOS NAND Circuit (2019 - 5 Marks)

Rule of Thumb: CMOS NAND = PMOS in Parallel (PUN), NMOS in Series (PDN).

Circuit Construction & Operation:

• Pull-Up Network (PUN): Three PMOS transistors ($P_A,P_B,P_C$) connected in parallel between $V_{DD}$ and Output $Y$.
• Pull-Down Network (PDN): Three NMOS transistors ($N_A,N_B,N_C$) connected in series between Output $Y$ and Ground.

Operational Truth:

• If ANY Input ($A,B,C$) is LOW (0V): At least one PMOS turns ON, connecting $Y$ to $V_{DD}$. At least one NMOS in the series stack turns OFF, breaking the path to Ground. Output $Y=\text{HIGH}$ ($V_{DD}$).
• If ALL Inputs ($A,B,C$) is HIGH (5V): All three PMOS turn OFF. All three NMOS turn ON, creating a continuous path from $Y$ to Ground. Output $Y=\text{LOW}$ ($0\text{V}$).

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2. Core Four Logic Gate Characteristics

10-Mark Exam Definitions (2015, 2016, 2018, 2021, 2024, 2025)

1. Fan-out: The maximum number of standard logic inputs that a single gate’s output can reliably drive without causing output voltage degradation below noise thresholds. $\text{Fan-out}=\min \left(\frac{I_{OH}}{I_{IH}},\frac{I_{OL}}{I_{IL}}\right)$

2. Propagation Delay ($t_p$): The average time delay required for a signal transition to propagate from gate input to gate output: $t_p=\frac{t_{pHL}+t_{pLH}}{2}$

3. Noise Margin: The maximum external noise voltage that can be added to an input signal without triggering an unintended change in output logic state: $\text{High Noise Margin: }N{M}_H=V_{OH(min)}-V_{IH(min)}$ $\text{Low Noise Margin: }N{M}_L=V_{IL(max)}-V_{OL(max)}$

4. Power Dissipation: The total electrical power consumed by a logic gate during operation, expressed in milliwatts (mW).

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3. Current Sourcing vs. Current Sinking

graph LR
    subgraph Current Sourcing HIGH Output
        Driver1[Driver Gate Output HIGH] -->|Sources Current IOH out of pin| Load1[Load Gate Inputs]
    end
    
    subgraph Current Sinking LOW Output
        Load2[Load Gate Inputs] -->|Sinks Current IOL into pin| Driver2[Driver Gate Output LOW to GND]
    end

• Current Sourcing ($I_{OH}$): Driver gate output is HIGH (Logic 1). Current flows out of driver output pin into load inputs.
• Current Sinking ($I_{OL}$): Driver gate output is LOW (Logic 0). Current flows from load inputs into driver output pin to Ground.

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4. Overview of Specialized Bipolar Families (ECL & I²L)

Syllabus Topic Overview: ECL & I²L Logic

Beyond TTL and CMOS, two specialized bipolar logic families exist in the theoretical syllabus:

• ECL (Emitter-Coupled Logic): A non-saturating bipolar logic family based on differential amplifiers. Because transistors are kept strictly out of saturation, ECL completely eliminates carrier storage delay, achieving sub-nanosecond propagation delays ($<1\text{ ns}$). It operates with negative supply voltages ($V_{EE}=-5.2\text{V}$) and has high power dissipation.
• I²L (Integrated Injection Logic): A high-density merged-transistor bipolar family that uses PNP current injectors and multi-collector NPN transistors. It operates at very low current levels, making it historically popular for dense bipolar microcircuits.

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Past Year Questions (PYQs)

• [PYQ 2019]: Draw 3-input CMOS NAND gate circuit and explain operation. (05 Marks)
• [PYQ 2016, 2018, 2021, 2024, 2025]: Define Fan-out, Propagation delay, Noise margin, Power dissipation, Current Sourcing. (08 to 10 Marks)