Related Concepts: 4.03 BJT as NOT Gate & Inverter Operation | 4.04 Diode Logic & DTL Logic Families | 4.05 TTL Logic Families & Open Collector Bus Systems

4.06 CMOS Logic & Logic Gate Characteristics

Concept Overview: CMOS & Bipolar Families

CMOS (Complementary Metal-Oxide Semiconductor) uses complementary pairs of p-channel (PMOS) and n-channel (NMOS) MOSFETs. It is the dominant VLSI logic family due to its near-zero static power consumption and extremely high integration density.

Beyond MOS logic, specialized bipolar logic families like ECL (Emitter-Coupled Logic) operate in non-saturating states to achieve maximum switching speeds.

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1. 3-Input CMOS NAND Gate Operation

Major PYQ Problem (PYQ 2019 — 05 marks)

Question (verbatim): Define Fan out and Noise margin characteristics of digital logic families and show the circuit of three inputs NAND gate using CMOS transistors.

Note the bundling — two definitions plus a circuit for only 5 marks. Keep the definitions to one line each (§4) and spend the time on a clean, labelled schematic.

Rule of Thumb: CMOS NAND = PMOS in Parallel (PUN), NMOS in Series (PDN).

Circuit Construction & Operation:

• Pull-Up Network (PUN): Three PMOS transistors ($P_A,P_B,P_C$) connected in parallel between $V_{DD}$ and Output $Y$.
• Pull-Down Network (PDN): Three NMOS transistors ($N_A,N_B,N_C$) connected in series between Output $Y$ and Ground.

graph TD
    subgraph CMOS 3-Input NAND Network Architecture
        VDD[Power Supply VDD] --> PUN[Pull-Up Network: 3 PMOS Transistors in PARALLEL]
        PUN --> OutY[Output Node Y]
        OutY --> PDN[Pull-Down Network: 3 NMOS Transistors in SERIES]
        PDN --> GND[Ground VSS]
    end

Operational Truth:

• If ANY Input ($A,B,C$) is LOW (0V): At least one PMOS turns ON, connecting $Y$ to $V_{DD}$. At least one NMOS in the series stack turns OFF, breaking the path to Ground. Output $Y=\text{HIGH}$ ($V_{DD}$).
• If ALL Inputs ($A,B,C$) are HIGH (5V): All three PMOS turn OFF. All three NMOS turn ON, creating a continuous path from $Y$ to Ground. Output $Y=\text{LOW}$ ($0\text{V}$).

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2. 3-Input CMOS NOR Gate Operation

Concept: CMOS NOR Rules

Rule of Thumb: CMOS NOR = PMOS in Series (PUN), NMOS in Parallel (PDN).

Circuit Construction & Operation:

• Pull-Up Network (PUN): Three PMOS transistors ($P_A,P_B,P_C$) connected in series between $V_{DD}$ and Output $Y$.
• Pull-Down Network (PDN): Three NMOS transistors ($N_A,N_B,N_C$) connected in parallel between Output $Y$ and Ground.

graph TD
    subgraph CMOS 3-Input NOR Network Architecture
        VDD[Power Supply VDD] --> PUN[Pull-Up Network: 3 PMOS Transistors in SERIES]
        PUN --> OutY[Output Node Y]
        OutY --> PDN[Pull-Down Network: 3 NMOS Transistors in PARALLEL]
        PDN --> GND[Ground VSS]
    end

Operational Truth:

• If ANY Input ($A,B,C$) is HIGH (5V): At least one NMOS turns ON, connecting Output $Y$ to Ground. At least one series PMOS turns OFF, disconnecting the path to $V_{DD}$. Output $Y=\text{LOW}$ ($0\text{V}$).
• If ALL Inputs ($A,B,C$) are LOW (0V): All three PMOS turn ON, creating a continuous path from $V_{DD}$ to Output $Y$. All three NMOS turn OFF, breaking all paths to Ground. Output $Y=\text{HIGH}$ ($V_{DD}$).

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3. Emitter-Coupled Logic (ECL) OR/NOR Gate Operation [Syllabus Week 8]

Foundational Concept (Outside Direct PYQ Scope)

Emitter-Coupled Logic (ECL) represents the pinnacle of high-speed silicon bipolar logic technology. While its non-saturating switching principles are essential digital foundations, detailed ECL circuit design calculations and schematics have never appeared in ECE 2103 past year question papers.

Emitter-Coupled Logic (ECL) is a non-saturating bipolar transistor logic family. By keeping the transistors out of the saturation region (operating strictly in the active and cut-off regions), it completely eliminates carrier storage time delays, making ECL the fastest semiconductor logic family (with sub-nanosecond propagation delays $<1\text{ ns}$).

Circuit Configuration & Logic Steering:

• Uses a differential amplifier input stage. Two input transistors ($T_A,T_B$) have their emitters tied together to a common emitter resistor $R_E$ connected to a negative supply $V_{EE}=-5.2\text{V}$.
• A reference transistor ($T_{REF}$) has its base connected to a fixed internal reference voltage $V_{BB}$.
• The collector outputs feed into emitter followers ($T_{OUT1},T_{OUT2}$) which act as low-impedance buffers providing the OR and NOR outputs simultaneously.

graph TD
    subgraph ECL Logic Steering
        Inputs[Inputs A, B] --> DiffAmp[Differential Input Transistors TA, TB]
        VBB[Reference Voltage VBB] --> RefTrans[Reference Transistor T_REF]
        DiffAmp & RefTrans --> CurrentSource[Common Current Source to VEE]
        DiffAmp -->|Collector 1| NOR[NOR Emitter Follower Output]
        RefTrans -->|Collector 2| OR[OR Emitter Follower Output]
    end

Operation:

• Inputs LOW (Logic 0): The input transistors ($T_A,T_B$) are cut off. The current through $R_E$ is steered entirely through $T_{REF}$ because $V_{BB}$ is higher than the input voltage. This drops the collector voltage of $T_{REF}$, pulling the OR output LOW. The collector of $T_A,T_B$ remains high, keeping the NOR output HIGH.
• ANY Input HIGH (Logic 1): The corresponding input transistor ($T_A$ or $T_B$) turns ON, steering the emitter current away from $T_{REF}$ (which now turns OFF). The collector of $T_A,T_B$ drops, pulling the NOR output LOW. The collector of $T_{REF}$ rises, pulling the OR output HIGH.

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4. Logic Gate Characteristics — The Definitions Question

This is the single most repeated question in the entire course

Some version of “Define the following terms that relate with the characteristics of digital logic families” has appeared in seven of the last ten papers — 2016, 2018, 2019, 2021, 2023, 2024 and 2025 — worth 6 to 10 marks each time. The examiner draws four terms from a fixed pool of five. Learn all five and you have covered every variant.

4.1 The Five Terms

1. Fan-out (asked every single time) The maximum number of standard logic inputs that a single gate output can reliably drive without its output voltage degrading past the valid logic thresholds. $\text{Fan-out}=\min \left(\frac{I_{OH}}{I_{IH}},\frac{I_{OL}}{I_{IL}}\right)$

2. Propagation Delay ($t_{pd}$) (asked every single time) The average time a signal transition takes to travel from a gate’s input to its output. It sets the maximum clock speed of any circuit built from that family. $t_{pd}=\frac{t_{pHL}+t_{pLH}}{2}$

3. Noise Margin (asked every single time) The maximum spurious voltage that can be added to an input without causing an unintended change of output state — i.e. how much electrical noise the gate tolerates before it misreads a logic level. $N{M}_H=V_{OH(min)}-V_{IH(min)}N{M}_L=V_{IL(max)}-V_{OL(max)}$

4. Power Dissipation (2016, 2018, 2021, 2024 — see the wording warning below) The total electrical power a gate consumes while operating, quoted in milliwatts per gate. It has two components: $P_D=P_{static}+P_{dynamic}=V_{CC}{I}_{CC}+\left(C_L{V}_{CC}^{2}f\right)$ In bipolar families (TTL, ECL) static power dominates; in CMOS static power is near zero and dissipation rises with switching frequency $f$.

5. Current Sourcing and Current Sinking (2025)

• Current sourcing ($I_{OH}$): the driver output is HIGH and current flows out of the output pin into the load inputs.
• Current sinking ($I_{OL}$): the driver output is LOW and current flows from the load inputs into the output pin, down to ground.

(Expanded with diagrams in §5.)

"Power distribution" — a recurring wording quirk in the papers

The 2016, 2018 and 2021 papers all print “Power distribution” as one of the four terms. There is no such standard logic-family characteristic; the intended term is unambiguously power dissipation. Answer it as power dissipation, and add a short parenthetical — “i.e. the power consumed per gate” — so the examiner can see you knew what was meant. 2024 prints it correctly as “power dissipation”.

4.2 Quick-Recall Table

Term	One-line definition	Formula	Asked in
Fan-out	How many inputs one output can drive	$\min (I_{OH}/I_{IH},I_{OL}/I_{IL})$	2016, 2018, 2019, 2021, 2023, 2024, 2025
Propagation delay	Input-to-output transition time	$(t_{pHL}+t_{pLH})/2$	2016, 2018, 2021, 2023, 2024, 2025
Noise margin	Tolerable noise before misreading a level	$N{M}_H=V_{OH}-V_{IH}$; $N{M}_L=V_{IL}-V_{OL}$	2016, 2018, 2019, 2021, 2023, 2024, 2025
Power dissipation	Power consumed per gate	$V_{CC}{I}_{CC}+C_L{V}_{CC}^{2}f$	2016, 2018, 2021, 2024
Current sourcing	Current flowing out of a HIGH output	$I_{OH}$	2025

How to score full marks here

Each term is worth roughly 2 marks, and a bare sentence typically earns 1. Give definition + formula + one-line significance for each — for example: “Fan-out is the maximum number of standard gate inputs one output can drive; $\text{Fan-out}=\min (I_{OH}/I_{IH},I_{OL}/I_{IL})$. Exceeding it pushes the output voltage out of the valid logic range and the circuit fails.” Three short clauses, full marks.

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5. Current Sourcing vs. Current Sinking

graph LR
    subgraph Current Sourcing HIGH Output
        Driver1[Driver Gate Output HIGH] -->|Sources Current IOH out of pin| Load1[Load Gate Inputs]
    end
    
    subgraph Current Sinking LOW Output
        Load2[Load Gate Inputs] -->|Sinks Current IOL into pin| Driver2[Driver Gate Output LOW to GND]
    end

• Current Sourcing ($I_{OH}$): Driver gate output is HIGH (Logic 1). Current flows out of driver output pin into load inputs.
• Current Sinking ($I_{OL}$): Driver gate output is LOW (Logic 0). Current flows from load inputs into driver output pin to Ground.

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6. Master Logic Family Comparison Table [Syllabus Week 8]

Parameter	Diode-Transistor Logic (DTL)	Transistor-Transistor Logic (TTL)	Emitter-Coupled Logic (ECL)	Complementary MOS (CMOS)
Basic Gate	NAND	NAND	OR / NOR	NAND / NOR
Transistor State	Saturating	Saturating	Non-Saturating (Active/Cut-off)	Enhancement (MOSFET)
Propagation Delay	Slow ($\approx 30\text{ ns}$)	Medium ($\approx 10\text{ ns}$)	Extremely Fast ($<1\text{ ns}$)	Medium-to-Fast ($1.5\to 15\text{ ns}$)
Power Dissipation	Medium ($\approx 12\text{ mW}$)	Medium ($\approx 10\text{ mW}$)	High ($\approx 25\text{ mW}$)	Extremely Low (near 0 static power)
Noise Margin	Medium ($\approx 0.7\text{V}$)	Medium ($\approx 0.4\text{V}$)	Low ($\approx 0.25\text{V}$)	High ($1.5\text{V}$ or $30\%$ of $V_{DD}$)
Fan-out	Low ($\approx 8$)	Medium ($\approx 10$)	High ($\approx 25$)	Very High ($>50$)

On IIL / I²L (Integrated Injection Logic)

The syllabus lists IIL alongside TTL, ECL and CMOS in Week 8, but it has never appeared in a past paper. In one line: I²L is a bipolar family that replaces resistors with current-injection transistors, giving very high packing density and very low power at the cost of speed. Know the name and that sentence; do not build a study session around it.

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7. Past Year Questions (PYQs)

PYQ Index for this note

Question (as asked)	Years	Marks	Solved in
Define: (i) Fan-out, (ii) Power distribution, (iii) Propagation delay, (iv) Noise margin	2016, 2018, 2021	8–10	§4
Define: (i) Fan-out, (ii) Propagation delay, (iii) Noise margin	2023	6	§4
Define: (i) Fan-out, (ii) Propagation delay, (iii) Power dissipation, (iv) Noise margin	2024	8	§4
Define: (i) Fan-out, (ii) Noise margin, (iii) Propagation delay, (iv) Current sourcing	2025	8	§4, §5
Define fan-out and noise margin, and show the circuit of a three-input NAND gate using CMOS transistors	2019	5	§1, §4
Describe the most important characteristics considered when evaluating the basic gate of digital logic families	2021	7	§4, §6

Pattern to notice: seven appearances in ten years makes this the highest-frequency question in the course, and it is pure recall — no derivation, no diagram (except in 2019). The term list barely changes: fan-out and noise margin appear in all seven, propagation delay in six. Roughly thirty minutes spent memorising the five definitions with their formulas secures 6–10 marks in essentially every paper.

The 2021 “most important characteristics” variant is the same content asked as an essay — answer it with the five terms from §4 plus a sentence on why each matters, then reference the family comparison table in §6.