Related Concepts: 4.03 BJT as NOT Gate & Inverter Operation | 4.05 TTL Logic Families & Open Collector Bus Systems | 4.06 CMOS Logic & Logic Gate Characteristics

4.04 Diode Logic & DTL Logic Families

Physical Hardware of Logic

Before analyzing complex integrated logic families like TTL, we study the simplest electronic gate models using semiconductor diodes (Diode Logic), and how they are paired with BJTs to create Diode-Transistor Logic (DTL).

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1. Diode Logic Gates (Diode OR & Diode AND) [Syllabus Week 7]

Foundational Concept (Outside Direct PYQ Scope)

Diode Logic (DL) gates are passive components that represent a foundational step in electronic logic evolution, but they are not directly tested as design problems in ECE 2103 examinations. They serve as required background for Diode-Transistor Logic (DTL).

Diode Logic (DL) is the most basic form of electronic logic gates, using PN-junction diodes as voltage-controlled switches.

A. The Diode OR Gate

Circuit Schematic:

Diodes are connected in parallel from each input node to the output node, with a pull-down resistor $R$ connected to Ground.

Diode OR Gate Schematic:
  Input A --->[ Diode DA (Anode -> Cathode) ]---+---> Output Y
                                                 |
  Input B --->[ Diode DB (Anode -> Cathode) ]---+
                                                 |
                                                 [ R ]
                                                 |
                                                GND

Operation:

• Case 1: Both Inputs A, B = LOW (0V): Diodes $D_A$ and $D_B$ are reverse-biased (OFF). No current flows. The output is pulled down to Ground through resistor $R$ ($Y\approx 0\text{V}⟹\text{Logic }0$).
• Case 2: Input A = HIGH (5V), B = LOW: Diode $D_A$ is forward-biased (ON) and conducts. Diode $D_B$ remains OFF. Current flows through $D_A$ and resistor $R$ to Ground. The output rises to input voltage minus one diode drop ($Y=V_{in}-V_D\approx 5\text{V}-0.7\text{V}=4.3\text{V}⟹\text{Logic }1$).

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B. The Diode AND Gate

Circuit Schematic:

Diodes are connected in parallel pointing from the output node back to the inputs, with a pull-up resistor $R$ connected to $V_{CC}$ (5V).

Diode AND Gate Schematic:
                             Vcc (5V)
                                |
                                [ R ]
                                |
  Input A <---[ Diode DA (Cathode <- Anode) ]------+---> Output Y
                                |
  Input B <---[ Diode DB (Cathode <- Anode) ]------+

Operation:

• Case 1: ANY Input (A or B) = LOW (0V): The corresponding diode is forward-biased (ON) and conducts current to Ground. This clamps the output node to Ground plus one diode drop ($Y=V_{in}+V_D\approx 0\text{V}+0.7\text{V}=0.7\text{V}⟹\text{Logic }0$).
• Case 2: BOTH Inputs A, B = HIGH (5V): Both diodes $D_A$ and $D_B$ are reverse-biased (OFF) because their cathodes are at $5\text{V}$. No current flows through the diodes. The output node is pulled up to $V_{CC}$ through resistor $R$ ($Y=V_{CC}=5\text{V}⟹\text{Logic }1$).

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2. NPN Silicon Transistor Characteristic Curves

Major Exam Problem (PYQ 2022 — 09 marks)

Question (verbatim): Draw and explain the Transistor Base and Transistor Collector characteristics for an npn silicon transistor.

This one is almost entirely a drawing question. Two labelled graphs with the three regions marked on the collector curves carry the bulk of the marks; the prose below is supporting explanation.

[GRAPH: Base input characteristics — I_B (µA, y-axis) vs V_BE (V, x-axis), one curve per V_CE value. Exponential diode shape; knee at V_BE ≈ 0.6–0.7 V. Source: Mano, Digital Design — logic families appendix]

[GRAPH: Collector output characteristics — I_C (mA, y-axis) vs V_CE (V, x-axis), family of curves for increasing I_B. Mark the three regions: saturation (steep rise, V_CE < 0.2 V), active (flat plateau), cut-off (I_B = 0, along the x-axis). Source: Mano, Digital Design — logic families appendix]

A. Base Input Characteristics ($I_B$ vs. $V_{BE}$)

• Curve Behavior: Operates like a forward-biased PN junction diode.
• Key Voltage: Negligible base current flows until $V_{BE}$ reaches cut-in voltage ($\approx 0.6\text{V}$). In saturation, $V_{BE(sat)}\approx 0.7\text{V}-0.8\text{V}$.

B. Collector Output Characteristics ($I_C$ vs. $V_{CE}$)

Divided into three distinct regions:

1. Cut-off Region: $I_B=0⟹I_C\approx 0,V_{CE}\approx V_{CC}$ (OFF Switch).
2. Active Region: Linear amplification region (not used in digital logic).
3. Saturation Region: $V_{CE}$ drops to $V_{CE(sat)}\approx 0.2\text{V}$, $I_C$ reaches maximum limit $I_{C(sat)}$ (ON Switch).

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3. DTL NAND Gate Saturation Proof

Major PYQ Proof (PYQ 2021, 2022 — 10 marks)

Question (verbatim): Show that the output transistor of the DTL gate of Fig. 4(d) goes into saturation when all inputs are high. Assume that $h_{FE}=20$.

(The 2022 paper prints “DLT gate” and references Fig. 4(b) — same question, typo and figure number aside.)

Given DTL NAND Parameters:

• $V_{CC}=5\text{V}$, $R_1=5\text{k}\Omega$, $R_2=5\text{k}\Omega$, $R_C=2\text{k}\Omega$, $h_{FE}=20$
• Diode drop $V_D=0.7\text{V}$, $V_{BE(sat)}=0.8\text{V}$, $V_{CE(sat)}=0.2\text{V}$

Proof Steps:

1. Input State: All inputs ($A,B,C$) are HIGH ($5\text{V}$) $⟹$ Input diodes are reverse-biased (OFF).

2. Node Voltage $V_P$ (Anode of level-shift diode $D_1$): $V_P=V_{D1}+V_{D2}+V_{BE(sat)}=0.7\text{V}+0.7\text{V}+0.8\text{V}=2.2\text{V}$

3. Current Calculations:

   • Current from $V_{CC}$ through $R_1$: $I_1=\frac{V_{CC}-V_P}{R_1}=\frac{5\text{V}-2.2\text{V}}{5\text{k}\Omega }=0.56\text{ mA}$
   • Current lost to ground through $R_2$: $I_2=\frac{V_{BE(sat)}}{R_2}=\frac{0.8\text{V}}{5\text{k}\Omega }=0.16\text{ mA}$
   • Base current entering transistor ($I_B$): $I_B=I_1-I_2=0.56\text{ mA}-0.16\text{ mA}=0.40\text{ mA}$

4. Saturation Check:

   • Maximum saturation collector current ($I_{C(sat)}$): $I_{C(sat)}=\frac{V_{CC}-V_{CE(sat)}}{R_C}=\frac{5\text{V}-0.2\text{V}}{2\text{k}\Omega }=2.4\text{ mA}$
   • Available collector current drive: $h_{FE}\times I_B=20\times 0.40\text{ mA}=8.0\text{ mA}$

5. Since $8.0\text{ mA}\gg 2.4\text{ mA}$ ($h_{FE}{I}_B\ge I_{C(sat)}$), the output transistor is driven deep into saturation. $■$

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4. Comparison Table: Diode Logic (DL) vs. Diode-Transistor Logic (DTL)

Feature	Diode Logic (DL)	Diode-Transistor Logic (DTL)
Logic Components	Diodes and resistors only.	Diodes, resistors, and Bipolar Junction Transistors (BJTs).
Signal Amplification	None (passive circuitry).	Active (transistor provides current amplification).
Signal Degradation	High. Output voltage drops by $V_D\approx 0.7\text{V}$ per stage (restricts cascading).	Near-zero. Transistor switches completely between $V_{CC}$ and $V_{CE(sat)}\approx 0.2\text{V}$, restoring signal levels.
Fan-out Capability	Very low (loading directly affects output voltage).	High (transistor amplifies current to drive multiple loads).
Logic Operations	AND, OR (cannot implement NOT/inversion).	NAND, NOR, NOT (BJT acts as an inverter).

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5. Past Year Questions (PYQs)

PYQ Index for this note

Question (as asked)	Years	Marks	Solved in
Draw and explain the Transistor Base and Transistor Collector characteristics for an npn silicon transistor	2022	9	§2
Show that the output transistor of the DTL gate goes into saturation when all inputs are high. Assume $h_{FE}=20$	2021, 2022	10	§3

Pattern to notice: the DTL saturation proof and the BJT inverter proof in 4.03 BJT as NOT Gate & Inverter Operation are the same proof structure — find $I_B$, find $I_{C(sat)}$, compare against $I_{C(sat)}/h_{FE}$. Together they account for 2016, 2019, 2021 and 2022, worth 10–13 marks each. Master one procedure, cover four papers.

Key difference to watch: in the BJT inverter, $I_B$ comes straight from $(V_{in}-V_{BE})/R_B$. In DTL you must first find the node voltage $V_P$ by stacking the two level-shifting diode drops plus $V_{BE(sat)}$, then subtract the current bled away through $R_2$. Skipping the $I_2$ subtraction is the classic error — it inflates $I_B$ and makes the saturation margin look larger than it is.

Not examined: the diode AND/OR gates in §1 have never been asked directly, but they are the building block the DTL input stage is made of — read them once, then move on.