Related Concepts: 4.01 Digital Systems & Signal Propagation | 4.04 Diode Logic & DTL Logic Families | 4.05 TTL Logic Families & Open Collector Bus Systems

4.03 BJT as NOT Gate & Inverter Operation

BJT Transistor Switch Concept

In digital logic, a Bipolar Junction Transistor (BJT) operates strictly as a digital switch driven between two extreme operating states:

1. Cut-off Region (OFF Switch): Base-Emitter junction reverse-biased $⟹I_B=0,I_C=0,V_{out}=V_{CC}$ (Logic HIGH).
2. Saturation Region (ON Switch): Base-Emitter junction forward-biased $⟹I_B\ge I_{B(sat)},V_{out}=V_{CE(sat)}\approx 0.2\text{V}$ (Logic LOW).

BJT Inverter Circuit Schematic:
                     Vcc (5V)
                        |
                        [ Rc ]
                        |
 Vin ---> [ Rb ] --->|/  Collector (Vout)
                     |\
                        v Emitter
                        |
                       GND

graph TD
    Input[Input Voltage Vin] --> Check{Vin Level}
    
    Check -->|Vin = LOW e.g. 0.2V| Cutoff[Cut-off Region: BE Junction OFF]
    Cutoff --> ICZero[Collector Current IC = 0]
    ICZero --> OutHigh[Output Vout = VCC = HIGH Logic 1]
    
    Check -->|Vin = HIGH e.g. 5V| Saturation[Saturation Region: BE Junction ON]
    Saturation --> ICSat[Max Collector Current IC-sat]
    ICSat --> OutLow[Output Vout = VCE-sat = 0.2V = LOW Logic 0]

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1. Mathematical Saturation & Cut-off Proof

Major Exam Numerical Problem (PYQ 2016, 2019 — 13 marks)

Question (verbatim): Show that the circuit shown in Fig. 4(b) behaves as an inverter with the following parameters: $R_C=1\text{ k}\Omega ,R_B=22\text{ k}\Omega ,V_{CC}=5\text{ V},h_{FE}=50,$ $H=5\text{ V (High level voltage)},L=0.2\text{ V (Low level voltage)}$

Standard silicon constants you are expected to supply yourself: $V_{BE(sat)}=0.7\text{ V}$, $V_{CE(sat)}=0.2\text{ V}$.

Read what is being asked. The question says “show that the circuit behaves as an inverter” — so the answer is not a single number. You must test both input levels and demonstrate that each produces the opposite output level.

Part A: Apply the LOW input, $V_{in}=L=0.2\text{ V}$

1. Base-emitter voltage $V_{BE}=0.2\text{ V}<0.7\text{ V}$ {below the silicon cut-in threshold, so the junction never turns on}.
2. The transistor is therefore in cut-off: $I_B=0$ and $I_C=0$.
3. With no collector current there is no drop across $R_C$: $V_{out}=V_{CC}-I_C{R}_C=5-(0)(1\text{k})=5\text{ V}=H(\text{Logic HIGH})$

$\therefore \text{Input }L⟹\text{Output }H$

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Part B: Apply the HIGH input, $V_{in}=H=5\text{ V}$

1. Actual base current supplied: $I_B=\frac{V_{in}-V_{BE(sat)}}{R_B}=\frac{5-0.7}{22\text{k}}=\frac{4.3}{22\text{k}}=0.195\text{ mA}$

2. Collector current if the transistor were saturated: $I_{C(sat)}=\frac{V_{CC}-V_{CE(sat)}}{R_C}=\frac{5-0.2}{1\text{k}}=\frac{4.8}{1\text{k}}=4.8\text{ mA}$

3. Minimum base current needed to sustain that: $I_{B(min)}=\frac{I_{C(sat)}}{h_{FE}}=\frac{4.8}{50}=0.096\text{ mA}$

4. Saturation test: $I_B=0.195\text{ mA}\ge I_{B(min)}=0.096\text{ mA}✓$ The available base current is roughly twice the minimum required, so the transistor is driven firmly into saturation.

5. Output: $V_{out}=V_{CE(sat)}=0.2\text{ V}=L(\text{Logic LOW})$

$\therefore \text{Input }H⟹\text{Output }L$

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Conclusion

$V_{in}$	Region	$V_{out}$	Logic
$L=0.2\text{ V}$	Cut-off	$5\text{ V}=H$	$0\to 1$
$H=5\text{ V}$	Saturation	$0.2\text{ V}=L$	$1\to 0$

Both input levels produce the complementary output level, and the output levels are the same $H$ and $L$ values as the inputs — so the stage can drive another identical stage. The circuit therefore behaves as an inverter (NOT gate). $■$

Where the marks are lost in this question

• Only testing one input. “Show that it behaves as an inverter” requires both cases. Solving only the saturation half typically caps you at about half the marks.
• Forgetting the saturation test. Computing $I_C=h_{FE}{I}_B$ and stopping is wrong — that formula only holds in the active region. You must compare $I_B$ against $I_{B(min)}$ to prove saturation, then state $V_{out}=V_{CE(sat)}$.
• Not stating $V_{BE(sat)}$ and $V_{CE(sat)}$. The paper does not give them. Write down that you are assuming $0.7\text{ V}$ and $0.2\text{ V}$ for silicon; assumptions stated explicitly earn credit.
• Closing the loop. Finish with an explicit sentence that output levels match input levels, so the gate is cascadable. That is the point of specifying $H$ and $L$ in the question.

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Past Year Questions (PYQs)

Question (as asked)	Years	Marks	Solved in
Show that the circuit of Fig. 4(b) behaves as an inverter with $R_C=1\text{k}\Omega$, $R_B=22\text{k}\Omega$, $V_{CC}=5\text{V}$, $h_{FE}=50$, $H=5\text{V}$, $L=0.2\text{V}$	2016, 2019	13	§1

Pattern to notice: identical wording and identical parameter values in both years — this is one of the most reliably repeated numericals in the paper, worth 13 marks. The method transfers directly to the DTL saturation proof in 4.04 Diode Logic & DTL Logic Families (2021, 2022), which uses the same $I_B\ge I_{C(sat)}/h_{FE}$ test with $h_{FE}=20$. Learn the procedure once and it covers roughly 23 marks across two questions.