Related Concepts: 01 Arithmetic Circuits, Multipliers & Comparators | 03 Tree Networks (Cascading MUX, Decoders & DeMUX) | 04 Programmable Logic Devices (ROM & PLA)

5.02 Code Converters & Data Routing Implementations

MSI Component Architecture

Medium Scale Integration (MSI) components—such as Decoders, Multiplexers (MUX), and Demultiplexers (DeMUX)—drastically reduce hardware gate counts and wiring complexity by replacing custom SSI gate networks.

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1. Core Data Routing Definitions

• Decoder: Converts binary information from $n$ input lines to a maximum of $2^n$ unique output lines {generates all minterms internally}.
• Multiplexer (MUX): Selects binary data from one of $2^n$ input lines and routes it to a single output controlled by $n$ select lines {Data Selector}.
• Demultiplexer (DeMUX): Takes data from a single input line and routes it to one of $2^n$ output lines controlled by $n$ select lines {Data Distributor}.

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2. Master Code Converter: 2,4,2,1 to 8,4,-2,-1

Major PYQ Problem (2017, 2019, 2020, 2023, 2024, 2025 - 14 Marks)

Question: Design a combinational circuit to convert a decimal digit from 2,4,2,1 code to 8,4,-2,-1 code.

Complete Conversion Truth Table:

Decimal	Inputs (2,4,2,1) $ABCD$	Outputs (8,4,-2,-1) $WXYZ$	Weight Check
0	0 0 0 0	0 0 0 0	$0=0$
1	0 0 0 1	0 1 1 1	$4-2-1=1$
2	0 0 1 0	0 1 1 0	$4-2-0=2$
3	0 0 1 1	0 1 0 1	$4-0-1=3$
4	0 1 0 0	0 1 0 0	$4-0-0=4$
5	1 0 1 1	1 0 1 1	$8-2-1=5$
6	1 1 0 0	1 0 1 0	$8-2-0=6$
7	1 1 0 1	1 0 0 1	$8-0-1=7$
8	1 1 1 0	1 0 0 0	$8-0-0=8$
9	1 1 1 1	1 1 1 1	$8+4-2-1=9$

• Don’t Care Conditions: Unused 2,4,2,1 binary combinations $0101\dots 1010⟹d=\Sigma d(5,6,7,8,9,10)$.

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3. Implementing Full-Adder using 4x1 Multiplexers

Major PYQ Problem (2021 - 10 Marks)

Inputs: $X,Y,Z$. Use two 4x1 MUXes (select lines $S_1=X,S_0=Y$).

graph TD
    subgraph 4x1 MUX Full-Adder Implementation
        S1[Select S1 = X] & S0[Select S0 = Y] --> MUX_Sum[MUX 1: Sum S]
        S1 & S0 --> MUX_Carry[MUX 2: Carry Out C]
        
        Z[Input Z] -->|I0=Z, I1=Z', I2=Z', I3=Z| MUX_Sum
        Z -->|I0=0, I1=Z, I2=Z, I3=1| MUX_Carry
    end

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4. Implementing Full-Adder using 3-to-8 Decoder

Major PYQ Problem (2019 - 7 Marks)

Inputs: $x,y,z$ connected to 3-to-8 decoder select lines.

• Sum Output ($S$): Connect decoder output pins 1, 2, 4, 7 to a 4-input OR gate $⟹S=\Sigma m(1,2,4,7)$.
• Carry Output ($C_{out}$): Connect decoder output pins 3, 5, 6, 7 to a second 4-input OR gate $⟹C_{out}=\Sigma m(3,5,6,7)$. $■$

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Past Year Questions (PYQs)

• [PYQ 2018, 2019]: Define Decoder, MUX, DeMUX. (06 Marks)
• [PYQ 2017, 2019, 2020, 2023, 2024, 2025]: 2,4,2,1 to 8,4,-2,-1 code converter. (14 Marks)
• [PYQ 2021]: Full-Adder using two 4x1 MUXes. (10 Marks)
• [PYQ 2019]: Full-Adder using 3-to-8 decoder and two OR gates. (07 Marks)