Related Concepts: 02 Code Converters & Data Routing Implementations | 03 Tree Networks (Cascading MUX, Decoders & DeMUX) | 04 Programmable Logic Devices (ROM & PLA)

5.01 Arithmetic Circuits, Multipliers & Comparators

Combinational Arithmetic Building Blocks

Combinational Arithmetic Circuits form the core of a CPU’s Arithmetic Logic Unit (ALU). Because combinational circuits have no memory elements, their outputs are functions solely of their present inputs.

graph TD
    subgraph 3 Half-Adder Functional Generator
        InA[Inputs A, B] --> HA1[Half-Adder 1: S1 = A ⊕ B, C1 = AB]
        HA1 & InC[Input C] --> HA2[Half-Adder 2: S2 = A ⊕ B ⊕ C = D, C2 = S1 • C = E]
        HA1 & InC --> HA3[Half-Adder 3: S3 = C1 ⊕ C = F, C3 = C1 • C = G]
    end

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1. The 4-Function Half-Adder Cascading Puzzle

Major Exam Problem: Implement 4 Functions using 3 Half-Adders (2015, 2018, 2019 - 12 Marks)

Question: Implement the following four Boolean functions using exactly three Half-Adder circuits:

• $D=A\oplus B\oplus C$
• $E=A^{\prime }BC+A{B}^{\prime }C$
• $F=AB{C}^{\prime }+(A^{\prime }+B^{\prime })C$
• $G=ABC$

Solution Step-by-Step:

1. Half-Adder 1 (HA1): Inputs $A$ and $B$.

   • Sum Output: $S_1=A\oplus B$
   • Carry Output: $C_1=AB$

2. Half-Adder 2 (HA2): Inputs $S_1$ and $C$.

   • Sum Output: $S_2=S_1\oplus C=(A\oplus B)\oplus C=\mathbf{A}\oplus \mathbf{B}\oplus \mathbf{C}=\mathbf{D}$
   • Carry Output: $C_2=S_1\cdot C=(A\oplus B)\cdot C=(A^{\prime }B+A{B}^{\prime })C={\mathbf{A}}^{\prime }\mathbf{BC}+\mathbf{A}{\mathbf{B}}^{\prime }\mathbf{C}=\mathbf{E}$

3. Half-Adder 3 (HA3): Inputs $C_1$ and $C$.

   • Sum Output: $S_3=C_1\oplus C=(AB)\oplus C=AB\cdot C^{\prime }+(AB{)}^{\prime }\cdot C=\mathbf{AB}{\mathbf{C}}^{\prime }+({\mathbf{A}}^{\prime }+{\mathbf{B}}^{\prime })\mathbf{C}=\mathbf{F}$
   • Carry Output: $C_3=C_1\cdot C=(AB)\cdot C=\mathbf{ABC}=\mathbf{G}■$

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2. Full-Adder to Full-Subtractor Conversion

The Single Inverter Trick (2020 - 10 Marks)

Question: Show that a Full-Adder can be converted to a Full-Subtractor with the addition of one inverter gate.

• Standard Full-Adder (FA): $Sum=X\oplus Y\oplus Z$, $C_{out}=XY+XZ+YZ$
• Standard Full-Subtractor (FS): $Diff=X\oplus Y\oplus Z$, $B_{out}=X^{\prime }Y+X^{\prime }Z+YZ$

Solution:

Connect an inverter to the Minuend input ($X$) before it enters the Full-Adder.

1. Input to FA becomes $X^{\prime }$.
2. Carry Out becomes: $C_{out\_new}=X^{\prime }Y+X^{\prime }Z+YZ={\mathbf{B}}_{\mathbf{out}}$ (matches Full-Subtractor Borrow Out).
3. Note: The Sum output becomes $Su{m}_{new}=X^{\prime }\oplus Y\oplus Z=(X\oplus Y\oplus Z{)}^{\prime }=\mathbf{Dif}{\mathbf{f}}^{\prime }$ (complement of Difference). $■$

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3. Carry Look-Ahead Mathematical Proof

Major Exam Proof: $C_{i+1}=G_i+P_i{C}_i$ (2018 - 10 Marks)

Question: Show that the output carry in a full-adder circuit can be expressed as $C_{i+1}=G_i+P_i{C}_i$.

Proof Steps:

1. Standard Full-Adder Carry Out: $C_{i+1}=A_i{B}_i+A_i{C}_i+B_i{C}_i=A_i{B}_i+C_i(A_i+B_i)$
2. Define Carry Generate ($G_i$): $G_i=A_i{B}_i$
3. Define Carry Propagate ($P_i$): $P_i=A_i\oplus B_i$
4. Substituting $G_i$ and $P_i$ yields: ${\mathbf{C}}_{\mathbf{i}+1}={\mathbf{G}}_{\mathbf{i}}+{\mathbf{P}}_{\mathbf{i}}{\mathbf{C}}_{\mathbf{i}}■$

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4. 2-Bit Binary Multiplier Circuit Design

Major PYQ Problem: $A_1{A}_0\times B_1{B}_0$ (2022 - 10 Marks)

Inputs: $A_1{A}_0$ and $B_1{B}_0$. Outputs: $P_3{P}_2{P}_1{P}_0$.

graph TD
    subgraph Multiplier Architecture
        P0[P0 = A0 • B0]
        AND1[A1 • B0] & AND2[A0 • B1] --> HA1[Half-Adder 1: Sum = P1, Carry = C1]
        AND3[A1 • B1] & HA1 --> HA2[Half-Adder 2: Sum = P2, Carry = P3]
    end

• Hardware Required: 4 AND gates and 2 Half-Adders.

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5. 4-Bit Magnitude Equality Comparator

Major PYQ Problem (2023, 2024, 2025 - 14 Marks)

Question: Design a circuit that compares two 4-bit numbers ($A,B$) and outputs $x=1$ if $A=B$, and $x=0$ if $A\ne B$.

Solution:

1. Bitwise Equality via XNOR: $x_i=A_i\odot B_i=A_i{B}_i+A_i^{\prime }{B}_i^{\prime }$
2. Total Equality ($A=B$): $\mathbf{x}={\mathbf{x}}_3\cdot {\mathbf{x}}_2\cdot {\mathbf{x}}_1\cdot {\mathbf{x}}_0=({\mathbf{A}}_3\odot {\mathbf{B}}_3)({\mathbf{A}}_2\odot {\mathbf{B}}_2)({\mathbf{A}}_1\odot {\mathbf{B}}_1)({\mathbf{A}}_0\odot {\mathbf{B}}_0)$
3. Circuit: Four 2-input XNOR gates feeding into one 4-input AND gate. $■$

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6. BCD Adder Design & Operation

Syllabus Context: Hardware Block Design

Design and operation of BCD adders is a standard 10-mark design question in ECE 2103 examinations.

A BCD Adder is a digital circuit that adds two BCD digits in parallel and produces a BCD sum digit.

The Correction Logic

The sum of two BCD digits ($A,B\le 9$) plus a carry-in ($C_{in}\le 1$) can range from $0$ to $19$.

• Standard 4-bit binary addition handles sums up to 15 without a carry-out.

• To convert a binary sum ($S_3{S}_2{S}_1{S}_0$ with carry $K$) into a valid BCD digit (where values $>9$ must generate a decimal carry and be offset by $+6$), we define a correction detection logic function $F$.

• Detection Rule: An overflow (sum $>9$) occurs if:

  1. $K=1$ (the binary sum is $\ge 16$).
  2. $S_3\cdot S_2=1$ (the binary sum is $12,13,14,$ or $15$).
  3. $S_3\cdot S_1=1$ (the binary sum is $10$ or $11$).

  $\mathbf{F}=\mathbf{K}+{\mathbf{S}}_3{\mathbf{S}}_2+{\mathbf{S}}_3{\mathbf{S}}_1$

• If $F=1$, we add binary $6_{10}=0110_2$ to the sum. The output carry for the next decimal stage is $F$.

Hardware Block Diagram:

graph TD
    subgraph BCD Adder Architecture
        InA[BCD Input A] & InB[BCD Input B] --> Adder1[4-Bit Binary Adder 1]
        Cin[Carry In] --> Adder1
        Adder1 --> BinSum[Binary Sum: S3 S2 S1 S0]
        Adder1 --> CarryK[Carry K]
        
        BinSum & CarryK --> Detect[Detection Logic: F = K + S3•S2 + S3•S1]
        
        Detect -->|F| CorrectionBit[Correction Value: 0 F F 0]
        
        BinSum & CorrectionBit --> Adder2[4-Bit Binary Adder 2]
        Adder2 --> BCDOut[Final BCD Sum Output]
        Detect --> CarryOut[Final BCD Carry Out Cout = F]
    end

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Past Year Questions (PYQs)

• [PYQ 2015, 2018, 2019]: Implement 4 functions using 3 Half-Adders. (12 Marks)
• [PYQ 2018]: Carry Look-Ahead proof $C_{i+1}=G_i+P_i{C}_i$. (10 Marks)
• [PYQ 2020]: FA to FS conversion using 1 inverter. (10 Marks)
• [PYQ 2022]: 2-bit binary multiplier circuit design. (10 Marks)
• [PYQ 2023, 2024, 2025]: 4-bit magnitude equality comparator ($A=B$). (14 Marks)
• [Syllabus / PYQ]: Explain BCD Adder operation and draw its circuit diagram. (10 Marks)