Related Concepts: 5.01 Arithmetic Circuits, Multipliers & Comparators | 5.02 Code Converters & Data Routing Implementations | 5.04 Programmable Logic Devices (ROM & PLA)

5.03 Tree Networks (Cascading MUX, Decoders & DeMUX)

Concept Overview: MSI Tree Networks

When required system line counts exceed single IC capacity, smaller Medium Scale Integration (MSI) components are cascaded into Tree Networks.

• Multiplexers: Level-1 outputs feed into Level-2 data inputs.
• Decoders & Demultiplexers: Master decoder uses MSBs to drive the Enable ($E$) pins of Slave decoders sharing LSB select lines.

graph TD
    subgraph 16-to-1 MUX Tree Architecture
        LSB[LSB Selects S1 S0] --> M1[4x1 MUX 1: D0-D3] & M2[4x1 MUX 2: D4-D7] & M3[4x1 MUX 3: D8-D11] & M4[4x1 MUX 4: D12-D15]
        M1 & M2 & M3 & M4 --> OutLevel1[4 Intermediate Outputs]
        OutLevel1 --> MUX_Final[Level 2: 4x1 MUX Driven by MSBs S3 S2]
        MUX_Final --> FinalOut[16-to-1 Output Y]
    end

---

1. 16-to-1 MUX using 4-to-1 MUXes

Major PYQ Problem (2016, 2017 - 8 Marks)

Question: Design a 16-to-1 Multiplexer using 4-to-1 Multiplexers.

Wiring Architecture:

• Level 1 (4 MUXes): Receives inputs $D_0\dots D_{15}$. LSB select lines $S_1,S_0$ are connected in parallel to all four MUXes.
• Level 2 (1 MUX): Receives the 4 intermediate outputs from Level 1. MSB select lines $S_3,S_2$ select which block output reaches final $Y$.
• Total Chips: $4+1=5\text{ MUXes}$.

---

2. Decoder Expansion Tree Networks

graph TD
    subgraph Master-Slave Decoder Expansion
        MSB[MSB Inputs A B] --> Master[Master 2x4 Decoder]
        Master -->|O0| E1[Enable Slave 1: Out 0-7]
        Master -->|O1| E2[Enable Slave 2: Out 8-15]
        Master -->|O2| E3[Enable Slave 3: Out 16-23]
        Master -->|O3| E4[Enable Slave 4: Out 24-31]
        
        LSB[LSB Inputs C D E] -->|Parallel Selects| E1 & E2 & E3 & E4
    end

A. 4-to-16 Decoder using Five 2-to-4 Decoders

• Master Decoder (1 Chip): Driven by MSBs $A,B$. Outputs $O_0\dots O_3$ drive Enable pins of Slaves.
• Slave Decoders (4 Chips): Driven by LSBs $C,D$ in parallel. Generates outputs $D_0\dots D_{15}$.

B. 5-to-32 Decoder using Four 3x8 and One 2x4 Decoders

• Master Decoder (2x4 Decoder): Driven by MSBs $A,B$. Outputs $O_0\dots O_3$ drive Enable pins of 3x8 Slaves.
• Slave Decoders (Four 3x8 Decoders): Driven by LSBs $C,D,E$ in parallel. Generates 32 outputs ($0\dots 31$).

---

3. 1x16 Demultiplexer using 2-to-4 Decoders

Major PYQ Problem (2023 - 7 Marks)

Question: Implement a 1x16 Demultiplexer using 2-to-4 decoders.

• Architecture: Wire five 2-to-4 decoders. Connect global Data Input ($D_{in}$) to the Enable pin of the Master decoder. MSBs $S_3,S_2$ drive Master select pins. LSBs $S_1,S_0$ drive Slave select pins in parallel.

---

Past Year Questions (PYQs)

Question (as asked)	Years	Marks	Solved in
Design a 16-to-1 multiplexer by using 4-to-1 multiplexers that can be used for a tree type network	2016 (12), 2017 (11)	11–12	§1
Construct a 4-to-16 line decoder with five 2-to-4 line decoders with enable	2021	10	§2
Construct a 5×32 decoder with four 3×8 decoders/demultiplexers and one 2×4 decoder. Use a block diagram construction	2024 (08), 2025 (09)	8–9	§2
Implement a 1×16 demultiplexer using only 2-to-4 decoders with enable inputs and no other logic gates. Clearly label all inputs, pins and outputs	2023	11	§3

Pattern to notice: a tree-network construction has appeared in six of the last ten papers (2016, 2017, 2021, 2023, 2024, 2025), worth 8–12 marks. Every one is the same idea: the low-order address bits drive the small blocks; the high-order bits drive a selector block whose outputs are wired to the ENABLE pins. Get the enable wiring right and the rest is drawing.

Read the constraints literally. The 2023 paper says “only 2-to-4 decoders with enable inputs and no other logic gates” and “clearly label all inputs, pins and outputs” — both are mark-bearing instructions. Adding a stray OR gate, or leaving pins unlabelled, loses marks even if the topology is right.

Count your blocks before drawing: a $2^n$-output tree from $2^k$-output blocks needs $2^{n-k}$ blocks plus one selector — e.g. 4-to-16 from 2-to-4 needs $4+1=5$ blocks, and 5×32 from 3×8 needs $4+1$. The question usually tells you the count, so use it to check your design.