Related Concepts: 5.01 Arithmetic Circuits, Multipliers & Comparators | 5.02 Code Converters & Data Routing Implementations | 5.05 Application-Specific Word Problems

5.04 Programmable Logic Devices (ROM & PLA)

PLD Classifications

Programmable Logic Devices (PLDs) replace custom SSI logic networks with dense arrays of AND and OR gates connected via programmable fuses.

• ROM: Fixed AND array (decoder) + Programmable OR array.
• PAL: Programmable AND array + Fixed OR array.
• PLA: Programmable AND array + Programmable OR array {maximum term-sharing flexibility}.

graph LR
    subgraph PLA Architecture
        Inputs[Inputs A B C] --> Buffers[Input Buffers / Inverters]
        Buffers --> ProgAND[Programmable AND Array: k Product Terms]
        ProgAND --> ProgOR[Programmable OR Array: m Outputs]
        ProgOR --> ProgInv[Programmable Output Inverters XOR/Fuses]
        ProgInv --> FinalOutputs[Outputs F1 F2]
    end

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0. Distinguishing ROM, PAL and PLA

Exam Theory Question (PYQ 2024, 2025 — 06 marks)

Question (verbatim): Distinguish the operation of ROM and PLA.

Feature	ROM	PAL	PLA
AND array	Fixed — a full decoder generating all $2^n$ minterms	Programmable	Programmable
OR array	Programmable	Fixed	Programmable
Product terms available	All $2^n$, whether needed or not	Limited, fixed per output	Chosen by the designer ($k$ terms)
Term sharing between outputs	Not applicable (every minterm exists)	Not possible — each OR is dedicated	Yes — one product term can feed several outputs
Simplification needed?	No — plug the truth table in directly	Yes	Yes, and both $F$ and $F^{\prime }$ should be tried
Silicon efficiency	Poor for sparse functions ($2^n$ rows always present)	Medium	Best — only the needed terms are built
Typical use	Look-up tables, code conversion, function tables	Simple glue logic	Multi-output logic with shared terms

The one-sentence answer

“A ROM has a fixed AND array (a decoder producing every minterm) with a programmable OR array, whereas a PLA has both arrays programmable — so a PLA builds only the product terms actually needed and can share them across outputs.” Follow with the term-sharing consequence and you have the full 6 marks.

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1. ROM Design: 3-Bit Input Square Generator

Five appearances, 8 to 13 marks

2015, 2017, 2020, 2021 and 2025 — identical wording each time.

Major PYQ Problem (PYQ 2015, 2020 — 12 marks; 2017 — 13 marks; 2021 — 08 marks; 2025 — 10 marks)

Question (verbatim): Design a combinational circuit using a ROM. The circuit accepts a 3-bit number and generates an output binary number equal to the square of the input number.

Solution & Optimization:

• Inputs: 3 bits ($A_2{A}_1{A}_0$, Max $7_{10}=111_2$).
• Outputs: Max $7^2=49_{10}=110001_2⟹6$ bits ($B_5{B}_4{B}_3{B}_2{B}_1{B}_0$).

Truth Table:

Decimal	Inputs ($A_2{A}_1{A}_0$)	Outputs ($B_5{B}_4{B}_3{B}_2{B}_1{B}_0$)
$0\to 0$	0 0 0	0 0 0 0 0 0
$1\to 1$	0 0 1	0 0 0 0 0 1
$2\to 4$	0 1 0	0 0 0 1 0 0
$3\to 9$	0 1 1	0 0 1 0 0 1
$4\to 16$	1 0 0	0 1 0 0 0 0
$5\to 25$	1 0 1	0 1 1 0 0 1
$6\to 36$	1 1 0	1 0 0 1 0 0
$7\to 49$	1 1 1	1 1 0 0 0 1

Circuit Hardware Optimization:

• Notice $B_0=A_0$ directly {no ROM needed}.
• Notice $B_1=0$ permanently {hardwired to Ground}.
• ROM Size Required: $2^3\times 4=8\times 4\text{ ROM}$ to generate $B_5,B_4,B_3,B_2$. $■$

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2. PLA Design: Shared Product Terms

Major PYQ Problem (PYQ 2015 — 12 marks; 2023 — 10 marks; 2024, 2025 — 11 marks)

Question (verbatim): A combinational circuit is defined by the functions: $F_1(A,B,C)=\sum (3,5,6,7)$ and $F_2(A,B,C)=\sum (0,2,4,7)$. Implement the circuit with a PLA having three inputs, four product terms, and two outputs.

Why you must simplify both $F$ and $F^{\prime }$

The constraint “four product terms” is the whole puzzle. Simplifying the two functions in their true form gives:

• $F_1=AB+AC+BC$ — three terms
• $F_2=A^{\prime }{C}^{\prime }+B^{\prime }{C}^{\prime }+ABC$ — three terms

That is six distinct product terms, with nothing shared — it does not fit. So try the complements as well and look for overlap:

• $F_1^{\prime }=A^{\prime }{B}^{\prime }+A^{\prime }{C}^{\prime }+B^{\prime }{C}^{\prime }$
• $F_2^{\prime }=A^{\prime }{B}^{\prime }C+A{B}^{\prime }{C}^{\prime }+\dots$ (no better)

Taking $F_1$ in complement form and $F_2$ in true form:

• $F_1^{\prime }=B^{\prime }{C}^{\prime }+A^{\prime }{C}^{\prime }+A^{\prime }{B}^{\prime }$
• $F_2=B^{\prime }{C}^{\prime }+A^{\prime }{C}^{\prime }+ABC$

Now $B^{\prime }{C}^{\prime }$ and $A^{\prime }{C}^{\prime }$ are shared, and the total distinct terms are exactly four: $B^{\prime }{C}^{\prime },A^{\prime }{C}^{\prime },A^{\prime }{B}^{\prime },ABC$. The PLA’s programmable output inverter restores $F_1$ from $F_1^{\prime }$.

Solution:

• $F_1^{\prime }=B^{\prime }{C}^{\prime }+A^{\prime }{C}^{\prime }+A^{\prime }{B}^{\prime }$
• $F_2=B^{\prime }{C}^{\prime }+A^{\prime }{C}^{\prime }+ABC$

The 4 distinct AND terms are: $B^{\prime }{C}^{\prime },A^{\prime }{C}^{\prime },A^{\prime }{B}^{\prime },ABC$.

PLA Program Table:

Product Term	Inputs ($A,B,C$)	Outputs ($F_1,F_2$)
1. $B^{\prime }{C}^{\prime }$	- 0 0	1 1
2. $A^{\prime }{C}^{\prime }$	0 - 0	1 1
3. $A^{\prime }{B}^{\prime }$	0 0 -	1 -
4. $ABC$	1 1 1	- 1
Output Mode:		C T

Reading the table: a - in the input columns means that variable is absent from the product term; a 1 in an output column means that term feeds that output’s OR gate. The bottom row records whether each output is taken in Complement or True form.

Where PLA marks are lost

• Not trying the complements. If your term count exceeds the budget, simplify $F_1^{\prime }$ and $F_2^{\prime }$ too and look for shared terms across the four candidate forms. The stated product-term limit is a hint that a complement is needed.
• Forgetting the output-mode row. The C/T line is not decoration — without it the circuit computes $F_1^{\prime }$, not $F_1$. It is usually worth marks on its own.
• Leaving the program table unlabelled. Draw the AND array, the OR array and the output inverters, and mark the programmed crosspoints. A bare list of equations does not demonstrate a PLA implementation.

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Past Year Questions (PYQs)

Question (as asked)	Years	Marks	Solved in
Design a combinational circuit using a ROM that accepts a 3-bit number and generates its square	2015, 2020 (12), 2017 (13), 2021 (8), 2025 (10)	8–13	§1
Implement $F_1=\sum (3,5,6,7)$, $F_2=\sum (0,2,4,7)$ with a PLA having three inputs, four product terms, two outputs	2015 (12), 2023 (10), 2024, 2025 (11)	10–12	§2
Distinguish the operation of ROM and PLA	2024, 2025	6	§0
Draw the block diagram of PLA	2018	5	§Abstract diagram
Define the following terms: … (iv) Decoder, (v) PLA	2017	part of 10	§Abstract, §0

Pattern to notice: ROM and PLA together appear in every paper from 2015 to 2025, worth 15–20 marks combined when both show up. They are also the two most formulaic design questions in the course:

• ROM — write the truth table, note that no simplification is required, state the ROM size. There is no K-map step at all.
• PLA — simplify all four forms ($F_1$, $F_1^{\prime }$, $F_2$, $F_2^{\prime }$), pick the combination that shares the most terms, then draw the program table with the C/T column.

Both questions reuse the same two functions year after year. Work §1 and §2 once each and the marks are effectively banked.