Related Concepts: 01 Arithmetic Circuits, Multipliers & Comparators | 02 Code Converters & Data Routing Implementations | 05 Application-Specific Word Problems

5.04 Programmable Logic Devices (ROM & PLA)

PLD Classifications

Programmable Logic Devices (PLDs) replace custom SSI logic networks with dense arrays of AND and OR gates connected via programmable fuses.

• ROM: Fixed AND array (decoder) + Programmable OR array.
• PAL: Programmable AND array + Fixed OR array.
• PLA: Programmable AND array + Programmable OR array {maximum term-sharing flexibility}.

graph LR
    subgraph PLA Architecture
        Inputs[Inputs A B C] --> Buffers[Input Buffers / Inverters]
        Buffers --> ProgAND[Programmable AND Array: k Product Terms]
        ProgAND --> ProgOR[Programmable OR Array: m Outputs]
        ProgOR --> ProgInv[Programmable Output Inverters XOR/Fuses]
        ProgInv --> FinalOutputs[Outputs F1 F2]
    end

---

1. ROM Design: 3-Bit Input Square Generator

Major PYQ Problem (2015, 2017, 2020, 2021, 2025 - 8 Marks)

Question: Design a combinational circuit using a ROM that accepts a 3-bit number and generates an output equal to its square.

Solution & Optimization:

• Inputs: 3 bits ($A_2{A}_1{A}_0$, Max $7_{10}=111_2$).
• Outputs: Max $7^2=49_{10}=110001_2⟹6$ bits ($B_5{B}_4{B}_3{B}_2{B}_1{B}_0$).

Truth Table:

Decimal	Inputs ($A_2{A}_1{A}_0$)	Outputs ($B_5{B}_4{B}_3{B}_2{B}_1{B}_0$)
$0\to 0$	0 0 0	0 0 0 0 0 0
$1\to 1$	0 0 1	0 0 0 0 0 1
$2\to 4$	0 1 0	0 0 0 1 0 0
$3\to 9$	0 1 1	0 0 1 0 0 1
$4\to 16$	1 0 0	0 1 0 0 0 0
$5\to 25$	1 0 1	0 1 1 0 0 1
$6\to 36$	1 1 0	1 0 0 1 0 0
$7\to 49$	1 1 1	1 1 0 0 0 1

Circuit Hardware Optimization:

• Notice $B_0=A_0$ directly {no ROM needed}.
• Notice $B_1=0$ permanently {hardwired to Ground}.
• ROM Size Required: $2^3\times 4=8\times 4\text{ ROM}$ to generate $B_5,B_4,B_3,B_2$. $■$

---

2. PLA Design: Shared Product Terms

Major PYQ Problem (2015, 2023, 2024, 2025 - 11 Marks)

Question: Implement $F_1(A,B,C)=\sum m(3,5,6,7)$ and $F_2(A,B,C)=\sum m(0,2,4,7)$ with a PLA having 3 inputs, 4 product terms, and 2 outputs.

Solution:

Simplify $F_1,F_1^{\prime }$ and $F_2,F_2^{\prime }$:

• $F_1^{\prime }=B^{\prime }{C}^{\prime }+A^{\prime }{C}^{\prime }+A^{\prime }{B}^{\prime }$
• $F_2=B^{\prime }{C}^{\prime }+A^{\prime }{C}^{\prime }+ABC$

Selecting $F_1^{\prime }$ (Complement form) and $F_2$ (True form) shares product terms $B^{\prime }{C}^{\prime }$ and $A^{\prime }{C}^{\prime }$! The 4 distinct AND terms are: $B^{\prime }{C}^{\prime },A^{\prime }{C}^{\prime },A^{\prime }{B}^{\prime },ABC$.

PLA Program Table:

Product Term	Inputs ($A,B,C$)	Outputs ($F_1,F_2$)
1. $B^{\prime }{C}^{\prime }$	- 0 0	1 1
2. $A^{\prime }{C}^{\prime }$	0 - 0	1 1
3. $A^{\prime }{B}^{\prime }$	0 0 -	1 -
4. $ABC$	1 1 1	- 1
Output Mode:		C T

---

Past Year Questions (PYQs)

• [PYQ 2017, 2024, 2025]: Distinguish between ROM and PLA. (06 Marks)
• [PYQ 2017, 2018]: Internal block diagram of PLA. (05 Marks)
• [PYQ 2015, 2017, 2020, 2021, 2025]: 3-bit square generator $8\times 4$ ROM design. (08 Marks)
• [PYQ 2015, 2023, 2024, 2025]: PLA design with shared product terms. (11 Marks)