02 Chapter 2 - Digital Codes & Error Detection (Merged)

Chapter 2: Digital Codes & Error Detection - Complete Study Notes

NotebookLM Ingestion Compilation

This merged document contains all 4 study notes for Chapter 2: Digital Codes & Error Detection from ECE 2103 Digital Electronics (Sharif Sir).

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Related Concepts: 02 Excess-3 Code & Self-Complementing Logic | 03 Gray Code & Code Conversions | 04 Error Control, Parity Generators & Checkers

2.01 BCD & Weighted Digital Codes

What is a Digital Code?

A Digital Code is a system of rules that assigns a unique pattern of binary bits (0s and 1s) to represent numbers, letters, symbols, or control commands.

Unlike pure binary number systems used for arithmetic, binary codes are engineered for specialized digital tasks such as decimal displays, error detection, data transmission, and mechanical position sensing.

graph TD
    Codes[Binary Digital Codes] --> Weighted[Weighted Positional Codes]
    Codes --> NonWeighted[Non-Weighted Codes]
    
    Weighted --> BCD8421[BCD / 8421 Code]
    Weighted --> W2421[2421 Self-Comp Code]
    Weighted --> W5211[5211 Code]
    Weighted --> W8421N[84-2-1 Negative Weight Code]
    
    NonWeighted --> XS3[Excess-3 Self-Comp Code]
    NonWeighted --> Gray[Gray Code / Single-Bit Change]
    NonWeighted --> ErrorCtrl[Parity / Error Control Codes]

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1. Distinction Between a Number System and a Code

Major Exam Theory Question (2018 - 4 Marks)

Question: Explain the fundamental differences between a Number System and a Code.

Aspect	Binary Number System	Binary Code
Fundamental Purpose	Designed for mathematical computation and quantitative representation.	Designed for human interface, data transmission, and hardware control.
Bit Position Weighting	Bit positions follow strict powers of 2 ($2^n,\dots ,2^2,2^1,2^0$).	Bit positions may have non-standard weights ($5,2,1,1$) or no weights at all.
Arithmetic Suitability	Directly supports standard addition, subtraction, and multiplication.	Unsuitable for direct arithmetic without specialized hardware conversion.
Bit Efficiency	Highly efficient; utilizes all $2^n$ binary combinations continuously.	Contains invalid/unused states {e.g., BCD skips 6 states out of 16}.
Representation Example	$12_{10}=1100_2$	$12_{10}=00010010_{\text{BCD}}$

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2. Weighted Positional Codes

A digital code is classified as Weighted if each bit position in a 4-bit group is assigned a fixed numerical weight ($w_3,w_2,w_1,w_0$). The represented decimal digit $D$ is calculated as: $D=(d_3\cdot w_3)+(d_2\cdot w_2)+(d_1\cdot w_1)+(d_0\cdot w_0)$

Comparison Table of Major 4-Bit Weighted Codes:

Decimal Digit	8421 (Standard BCD)	2421 Code	5211 Code	84-2-1 Code
0	0000	0000	0000	0000
1	0001	0001	0001	0111
2	0010	0010	0011	0110
3	0011	0011	0100	0101
4	0100	0100	0101	0100
5	0101	1011	1000	1011
6	0110	1100	1001	1010
7	0111	1101	1011	1001
8	1000	1110	1100	1000
9	1001	1111	1111	1111

Terminology & Concept Breakdown

• 8421 (BCD): The standard Binary Coded Decimal system. Uses standard binary weights for digits 0 to 9. States 1010 to 1111 ($10$ to $15$) are invalid.
• 2421 Code: A weighted self-complementing code where the sum of bit weights equals $9$.
• 5211 Code: A weighted code where the MSB carries a weight of $5$.
• 84-2-1 Code: A negative-weight code where the last two bits carry negative weights ($-2$ and $-1$).

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3. PYQ Numerical Solution: 5211 Code Conversion

Major Exam Problem: Convert $(605{)}_{10}$ into 5211 Weighted Code (2018 - 8 Marks)

Solution:

To convert a multi-digit decimal number into 5211 code, convert each decimal digit independently into its corresponding 4-bit 5211 code group from the lookup table:

1. Digit 6: $5211⟹5(1)+2(0)+1(0)+1(1)=6⟹1001_2$
2. Digit 0: $5211⟹5(0)+2(0)+1(0)+1(0)=0⟹0000_2$
3. Digit 5: $5211⟹5(1)+2(0)+1(0)+1(0)=5⟹1000_2$

$\text{Final 5211 Code Result: }(100100001000{)}_{\text{5211}}■$

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Past Year Questions (PYQs)

• [PYQ 2018]: Explain the difference between a Number System and a Code. (04 Marks)
• [PYQ 2018]: Convert decimal numbers into 5211 weighted code (e.g., $(605{)}_{10}$). (08 Marks)
• [PYQ 2019]: Conversions for BCD, 2421, 5211, and 84-2-1 codes. (08 Marks)

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Related Concepts: 01 BCD & Weighted Digital Codes | 03 Gray Code & Code Conversions | 04 Error Control, Parity Generators & Checkers

2.02 Excess-3 Code & Self-Complementing Logic

What is a Self-Complementing Code?

A 4-bit binary code is defined as Self-Complementing if the 1’s complement {bitwise inversion: $0\to 1,1\to 0$} of any decimal digit’s code word yields the exact code word of its 9’s decimal complement ($9-N$).

$\text{Code}(9-N)=\overline{\text{Code}(N)}$

graph LR
    subgraph Self-Complementing Symmetry
        D2[Decimal Digit 2: 0101] -->|Bitwise Inversion| InvD2[1's Comp: 1010]
        InvD2 -->|Equals| D7[Decimal Digit 7 = 9 - 2: 1010]
    end

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1. Mathematical Proof: Excess-3 is a Self-Complementing Code

Major Exam Proof (2021, 2023, 2025 - 8 to 10 Marks)

Question: Prove mathematically that Excess-3 (XS-3) code is a self-complementing code.

Step-by-Step Proof:

1. Definition of Excess-3 Code: The Excess-3 code word for any decimal digit $N$ ($0\le N\le 9$) is constructed by adding $3_{10}=0011_2$ to its standard 4-bit binary equivalent: $\text{XS-3}(N)=N+3$

2. Evaluating the 9’s Complement of $N$ ($9-N$): The Excess-3 code word for the 9’s complement of $N$ is: $\text{XS-3}(9-N)=(9-N)+3=12-N$

3. Evaluating the 1’s Complement of $\text{XS-3}(N)$: Taking the bitwise 1’s complement of a 4-bit number is mathematically equivalent to subtracting it from $15_{10}$ ($1111_2$): $\overline{\text{XS-3}(N)}=15-\text{XS-3}(N)$ Substituting $\text{XS-3}(N)=N+3$: $\overline{\text{XS-3}(N)}=15-(N+3)=15-N-3=12-N$

4. Comparing Results: $\text{XS-3}(9-N)=12-N$ $\overline{\text{XS-3}(N)}=12-N$ $\therefore \text{XS-3}(9-\mathbf{N})=\overline{\text{XS-3}(\mathbf{N})}■$

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2. Complete 9’s Complement Symmetry Table

Decimal Digit ($N$)	BCD (8421)	Excess-3 Code ($\text{BCD}+3$)	1’s Comp of XS-3	9’s Comp Digit ($9-N$)	XS-3 Code of ($9-N$)
0	0000	0011	1100	9	1100
1	0001	0100	1011	8	1011
2	0010	0101	1010	7	1010
3	0011	0110	1001	6	1001
4	0100	0111	1000	5	1000
5	0101	1000	0111	4	0111
6	0110	1001	0110	3	0110
7	0111	1010	0101	2	0101
8	1000	1011	0100	1	0100
9	1001	1100	0011	0	0011

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3. Design: BCD to Excess-3 Code Converter

Major Exam Design Problem (2018 - 10 Marks)

Question: Design a combinational logic circuit to convert a 4-bit BCD input ($A,B,C,D$) to a 4-bit Excess-3 code output ($W,X,Y,Z$).

Boolean Function Derivation (K-Map Simplification):

• Inputs: $A,B,C,D$ (Don’t care conditions $X=d(10,11,12,13,14,15)$).
• Outputs: $W,X,Y,Z$.

1. Output $Z$ (LSB): $Z={\mathbf{D}}^{\prime }$
2. Output $Y$: $Y=CD+C^{\prime }{D}^{\prime }=(\mathbf{C}\oplus \mathbf{D}{)}^{\prime }$
3. Output $X$: $X=B^{\prime }C+B^{\prime }D+B{C}^{\prime }{D}^{\prime }=\mathbf{B}\oplus (\mathbf{C}+\mathbf{D})$
4. Output $W$ (MSB): $W=A+BC+BD=\mathbf{A}+\mathbf{B}(\mathbf{C}+\mathbf{D})$

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Past Year Questions (PYQs)

• [PYQ 2017, 2021, 2023, 2025]: Define self-complementary code. (04 Marks)
• [PYQ 2021, 2023, 2025]: Prove mathematically that Excess-3 code is a self-complementary code. (08-10 Marks)
• [PYQ 2018]: Design a BCD to Excess-3 code converter circuit. (10 Marks)

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Related Concepts: 01 BCD & Weighted Digital Codes | 02 Excess-3 Code & Self-Complementing Logic | 04 Error Control, Parity Generators & Checkers

2.03 Gray Code & Code Conversions

What is Gray Code?

Gray Code {also called Reflected Binary Code} is a 4-bit (or $N$-bit) non-weighted binary coding system.

Its defining property is: “A binary coding system in which ONLY ONE BIT changes at a time between any two consecutive code words.”

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1. Why is it Called “Reflected” Code?

The code is named “reflected” because the sequence of code words for the second half of any $N$-bit Gray code sequence is the exact mirror image {reflection} of the first half, with the exception of the MSB which is inverted from 0 to 1.

2-Bit Gray Code Reflection Example:
Decimal 0:  0 0  ---| First half (MSB = 0)
Decimal 1:  0 1  ---|
-------------------- Reflection Axis
Decimal 2:  1 1  ---| Second half (MSB = 1, LSB reflected: 1 then 0)
Decimal 3:  1 0  ---|

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2. Conversion Algorithms

Conversions between pure Binary and Gray code rely entirely on the Exclusive-OR (XOR, $\oplus$) operation.

graph TD
    subgraph Binary to Gray Algorithm
        B3[B3 MSB] --> G3[G3 = B3]
        B3 & B2[B2] -->|XOR| G2[G2 = B3 ⊕ B2]
        B2 & B1[B1] -->|XOR| G1[G1 = B2 ⊕ B1]
        B1 & B0[B0 LSB] -->|XOR| G0[G0 = B1 ⊕ B0]
    end

graph TD
    subgraph Gray to Binary Algorithm
        g3[G3 MSB] --> b3[B3 = G3]
        b3 & g2[G2] -->|XOR| b2[B2 = B3 ⊕ G2]
        b2 & g1[G1] -->|XOR| b1[B1 = B2 ⊕ G1]
        b1 & g0[G0 LSB] -->|XOR| b0[B0 = B1 ⊕ G0]
    end

A. Binary to Gray Code Conversion

Given an $N$-bit Binary number ($B_{N-1}\dots B_0$), compute Gray bits ($G_{N-1}\dots G_0$):

• MSB Rule: $G_{N-1}=B_{N-1}$
• Subsequent Bits Rule: $G_i=B_{i+1}\oplus B_i$ for $i=N-2,\dots ,0$.

B. Gray Code to Binary Conversion

Given an $N$-bit Gray code ($G_{N-1}\dots G_0$), compute Binary bits ($B_{N-1}\dots B_0$):

• MSB Rule: $B_{N-1}=G_{N-1}$
• Subsequent Bits Rule: $B_i=B_{i+1}\oplus G_i$ for $i=N-2,\dots ,0$.

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3. Design: 4-Bit Reflected Code to Binary Converter Circuit

Major Exam Design Problem (2024 - 10 Marks)

Question: Design a combinational logic circuit that converts a 4-bit reflected code (Gray code) number to a 4-bit binary number using XOR gates.

Circuit Equations & Architecture:

$B_3=G_3$ $B_2=G_3\oplus G_2$ $B_1=B_2\oplus G_1$ $B_0=B_1\oplus G_0$

The circuit consists of a cascading chain of three 2-input XOR gates:

• $G_3$ passes straight to output $B_3$.
• $G_3\oplus G_2\to B_2$.
• $B_2\oplus G_1\to B_1$.
• $B_1\oplus G_0\to B_0$.

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Past Year Questions (PYQs)

• [PYQ 2017]: Define Reflected code. (04 Marks)
• [PYQ 2018]: Convert $(605{)}_{10}$ into Gray code number. (Binary: $1001011101_2⟹1101110011_{\text{Gray}}$). (12 Marks)
• [PYQ 2024]: Design a 4-bit reflected code to binary converter circuit using XOR gates. (10 Marks)

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Related Concepts: 01 BCD & Weighted Digital Codes | 02 Excess-3 Code & Self-Complementing Logic | 03 Gray Code & Code Conversions

2.04 Error Control, Parity Generators & Checkers

Error Control Concepts

During serial data transmission over noisy communication channels, electromagnetic interference can cause bit inversion errors {$0\to 1$ or $1\to 0$}.

To safeguard data integrity, systems employ Error Control Codes by appending redundant check bits to transmitted data packets.

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1. Error Detecting vs. Error Correcting Codes

Major Exam Theory Question (2017, 2018 - 4 Marks)

Question: Explain the fundamental differences between Error Detecting codes and Error Correcting codes.

Parameter	Error Detecting Codes	Error Correcting Codes
Primary Function	Detects the presence of errors during transmission.	Detects the error AND automatically determines its bit location to correct it.
Action on Error	Flags error to receiver; requires retransmission.	Automatically corrects error without requesting retransmission.
Redundancy Overhead	Low overhead; requires few redundant bits {e.g., 1 parity bit}.	High overhead; requires multiple redundant check bits {e.g., Hamming distance}.
Implementation Complexity	Simple hardware {cascaded XOR gates}.	Complex logic {syndrome decoders & bit-flipping networks}.
Standard Examples	Parity bits, Checksums, CRC.	Hamming Code, Reed-Solomon Code, BCH Code.

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2. Parity Architecture & Operation

graph LR
    subgraph Transmitter End
        DataTx[Data Bits: x y z] --> GenXOR[Parity Generator Logic]
        GenXOR --> Packet[Transmitted Packet: x y z P]
    end
    
    Packet -->|Serial Channel| RxPacket[Received Packet: x' y' z' P']
    
    subgraph Receiver End
        RxPacket --> CheckXOR[Parity Checker Logic]
        CheckXOR -->|C = 0| NoError[No Error Detected]
        CheckXOR -->|C = 1| ErrorDet[Bit Error Flagged!]
    end

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3. Even Parity Generator & Checker

• Even Parity Rule: The parity bit $P$ is generated so that the total count of 1s in $(x,y,z,P)$ is always EVEN.
• 3-Bit Generator (Transmitter): $P=x\oplus y\oplus z$
• 4-Bit Checker (Receiver): $C=x\oplus y\oplus z\oplus P$
  • $C=0⟹\text{No Error}$
  • $C=1⟹\text{Error Detected!}$

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4. Design: 3-Bit Odd Parity Generator & 4-Bit Checker

Major Exam Design Problem (2022 - 8 Marks, 2025 - 10 Marks)

Question: Design a 3-bit parity generator and 4-bit parity checker circuit using an odd parity bit.

Part A: 3-Bit Odd Parity Generator (Transmitter)

• Logic Rule: Generates $P$ such that total 1s in $(x,y,z,P)$ is ODD. If $(x,y,z)$ has an even number of 1s, $P$ must be 1.

Truth Table:

Input Message ($x,y,z$)	Generated Odd Parity Bit ($P$)
0 0 0	1
0 0 1	0
0 1 0	0
0 1 1	1
1 0 0	0
1 0 1	1
1 1 0	1
1 1 1	0

Boolean Function:

The minterms for $P$ are $\Sigma m(0,3,5,6)$, which is the exact inverse of a 3-input XOR function {an XNOR function}: $P=(x\oplus y\oplus z{)}^{\prime }=x\oplus y\odot z$

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Part B: 4-Bit Odd Parity Checker (Receiver)

• Logic Rule: Evaluates received bits $(x,y,z,P)$. If total 1s is EVEN, an error has occurred $⟹$ Error output $C=1$.

Boolean Function:

$C=(x\oplus y\oplus z\oplus P{)}^{\prime }=x\odot y\odot z\odot P$ Implemented by cascading three 2-input XNOR gates.

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5. Critical Limitations of Parity Error Checking

Limitations of Simple Parity

1. Odd-Bit Error Detection Only: Parity can ONLY detect an odd number of bit errors {1, 3, 5 flipped bits}.
2. Fails on Even-Bit Errors: If an even number of bits flip {e.g., 2 bits change state}, total parity remains unchanged, and $C$ remains $0$ {error undetected}.
3. No Correction Capability: Parity indicates that an error occurred, but cannot identify which bit flipped.

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Past Year Questions (PYQs)

• [PYQ 2017]: Define Error Detection Code. (04 Marks)
• [PYQ 2018]: Differences between Error Detecting and Error Correcting codes. (04 Marks)
• [PYQ 2015, 2020, 2023, 2024]: 4-bit even parity checker design. (08 Marks)
• [PYQ 2022, 2025]: Design 3-bit generator & 4-bit checker using odd parity bit. (08 to 10 Marks)

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