Related Concepts: 01 BCD & Weighted Digital Codes | 02 Excess-3 Code & Self-Complementing Logic | 03 Gray Code & Code Conversions

2.04 Error Control, Parity Generators & Checkers

Error Control Concepts

During serial data transmission over noisy communication channels, electromagnetic interference can cause bit inversion errors {$0\to 1$ or $1\to 0$}.

To safeguard data integrity, systems employ Error Control Codes by appending redundant check bits to transmitted data packets.

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1. Error Detecting vs. Error Correcting Codes

Major Exam Theory Question (2017, 2018 - 4 Marks)

Question: Explain the fundamental differences between Error Detecting codes and Error Correcting codes.

Parameter	Error Detecting Codes	Error Correcting Codes
Primary Function	Detects the presence of errors during transmission.	Detects the error AND automatically determines its bit location to correct it.
Action on Error	Flags error to receiver; requires retransmission.	Automatically corrects error without requesting retransmission.
Redundancy Overhead	Low overhead; requires few redundant bits {e.g., 1 parity bit}.	High overhead; requires multiple redundant check bits {e.g., Hamming distance}.
Implementation Complexity	Simple hardware {cascaded XOR gates}.	Complex logic {syndrome decoders & bit-flipping networks}.
Standard Examples	Parity bits, Checksums, CRC.	Hamming Code, Reed-Solomon Code, BCH Code.

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2. Parity Architecture & Operation

graph LR
    subgraph Transmitter End
        DataTx[Data Bits: x y z] --> GenXOR[Parity Generator Logic]
        GenXOR --> Packet[Transmitted Packet: x y z P]
    end
    
    Packet -->|Serial Channel| RxPacket[Received Packet: x' y' z' P']
    
    subgraph Receiver End
        RxPacket --> CheckXOR[Parity Checker Logic]
        CheckXOR -->|C = 0| NoError[No Error Detected]
        CheckXOR -->|C = 1| ErrorDet[Bit Error Flagged!]
    end

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3. Even Parity Generator & Checker

• Even Parity Rule: The parity bit $P$ is generated so that the total count of 1s in $(x,y,z,P)$ is always EVEN.
• 3-Bit Generator (Transmitter): $P=x\oplus y\oplus z$
• 4-Bit Checker (Receiver): $C=x\oplus y\oplus z\oplus P$
  • $C=0⟹\text{No Error}$
  • $C=1⟹\text{Error Detected!}$

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4. Design: 3-Bit Odd Parity Generator & 4-Bit Checker

Major Exam Design Problem (2022 - 8 Marks, 2025 - 10 Marks)

Question: Design a 3-bit parity generator and 4-bit parity checker circuit using an odd parity bit.

Part A: 3-Bit Odd Parity Generator (Transmitter)

• Logic Rule: Generates $P$ such that total 1s in $(x,y,z,P)$ is ODD. If $(x,y,z)$ has an even number of 1s, $P$ must be 1.

Truth Table:

Input Message ($x,y,z$)	Generated Odd Parity Bit ($P$)
0 0 0	1
0 0 1	0
0 1 0	0
0 1 1	1
1 0 0	0
1 0 1	1
1 1 0	1
1 1 1	0

Boolean Function:

The minterms for $P$ are $\Sigma m(0,3,5,6)$, which is the exact inverse of a 3-input XOR function {an XNOR function}: $P=(x\oplus y\oplus z{)}^{\prime }=x\oplus y\odot z$

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Part B: 4-Bit Odd Parity Checker (Receiver)

• Logic Rule: Evaluates received bits $(x,y,z,P)$. If total 1s is EVEN, an error has occurred $⟹$ Error output $C=1$.

Boolean Function:

$C=(x\oplus y\oplus z\oplus P{)}^{\prime }=x\odot y\odot z\odot P$ Implemented by cascading three 2-input XNOR gates.

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5. Critical Limitations of Parity Error Checking

Limitations of Simple Parity

1. Odd-Bit Error Detection Only: Parity can ONLY detect an odd number of bit errors {1, 3, 5 flipped bits}.
2. Fails on Even-Bit Errors: If an even number of bits flip {e.g., 2 bits change state}, total parity remains unchanged, and $C$ remains $0$ {error undetected}.
3. No Correction Capability: Parity indicates that an error occurred, but cannot identify which bit flipped.

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Past Year Questions (PYQs)

• [PYQ 2017]: Define Error Detection Code. (04 Marks)
• [PYQ 2018]: Differences between Error Detecting and Error Correcting codes. (04 Marks)
• [PYQ 2015, 2020, 2023, 2024]: 4-bit even parity checker design. (08 Marks)
• [PYQ 2022, 2025]: Design 3-bit generator & 4-bit checker using odd parity bit. (08 to 10 Marks)