Related Concepts: 03 BJT as NOT Gate & Inverter Operation | 05 TTL Logic Families & Open Collector Bus Systems | 06 CMOS Logic & Logic Gate Characteristics

4.04 NPN Transistor Basics & DTL Logic

Physical Hardware of Logic

Before analyzing complex integrated logic families like TTL, understanding the current-voltage ($I-V$) characteristics of an NPN Bipolar Junction Transistor (BJT) and its application in Diode-Transistor Logic (DTL) is required.

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1. NPN Silicon Transistor Characteristic Curves

A. Base Input Characteristics ($I_B$ vs. $V_{BE}$)

• Curve Behavior: Operates like a forward-biased PN junction diode.
• Key Voltage: Negligible base current flows until $V_{BE}$ reaches cut-in voltage ($\approx 0.6\text{V}$). In saturation, $V_{BE(sat)}\approx 0.7\text{V}-0.8\text{V}$.

B. Collector Output Characteristics ($I_C$ vs. $V_{CE}$)

Divided into three distinct regions:

1. Cut-off Region: $I_B=0⟹I_C\approx 0,V_{CE}\approx V_{CC}$ (OFF Switch).
2. Active Region: Linear amplification region (not used in digital logic).
3. Saturation Region: $V_{CE}$ drops to $V_{CE(sat)}\approx 0.2\text{V}$, $I_C$ reaches maximum limit $I_{C(sat)}$ (ON Switch).

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2. DTL NAND Gate Saturation Proof

Major PYQ Proof: DTL Gate Saturation ( $h_{FE}=20$) (2021, 2022 - 10 Marks)

Given DTL NAND Parameters:

• $V_{CC}=5\text{V}$, $R_1=5\text{k}\Omega$, $R_2=5\text{k}\Omega$, $R_C=2\text{k}\Omega$, $h_{FE}=20$
• Diode drop $V_D=0.7\text{V}$, $V_{BE(sat)}=0.8\text{V}$, $V_{CE(sat)}=0.2\text{V}$

Proof Steps:

1. Input State: All inputs ($A,B,C$) are HIGH ($5\text{V}$) $⟹$ Input diodes are reverse-biased (OFF).

2. Node Voltage $V_P$ (Anode of level-shift diode $D_1$): $V_P=V_{D1}+V_{D2}+V_{BE(sat)}=0.7\text{V}+0.7\text{V}+0.8\text{V}=2.2\text{V}$

3. Current Calculations:

   • Current from $V_{CC}$ through $R_1$: $I_1=\frac{V_{CC}-V_P}{R_1}=\frac{5\text{V}-2.2\text{V}}{5\text{k}\Omega }=0.56\text{ mA}$
   • Current lost to ground through $R_2$: $I_2=\frac{V_{BE(sat)}}{R_2}=\frac{0.8\text{V}}{5\text{k}\Omega }=0.16\text{ mA}$
   • Base current entering transistor ($I_B$): $I_B=I_1-I_2=0.56\text{ mA}-0.16\text{ mA}=0.40\text{ mA}$

4. Saturation Check:

   • Maximum saturation collector current ($I_{C(sat)}$): $I_{C(sat)}=\frac{V_{CC}-V_{CE(sat)}}{R_C}=\frac{5\text{V}-0.2\text{V}}{2\text{k}\Omega }=2.4\text{ mA}$
   • Available collector current drive: $h_{FE}\times I_B=20\times 0.40\text{ mA}=8.0\text{ mA}$

5. Since $8.0\text{ mA}\gg 2.4\text{ mA}$ ($h_{FE}{I}_B\ge I_{C(sat)}$), the output transistor is driven deep into saturation. $■$

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Past Year Questions (PYQs)

• [PYQ 2022]: Draw and explain Transistor Base and Collector characteristics. (09 Marks)
• [PYQ 2021, 2022]: DTL gate output transistor saturation proof ($h_{FE}=20$). (10 Marks)