Related Concepts: 1.01 Positional Number Systems & Base Conversions | 1.02 Base Complements & Subtraction Mechanics | 2.04 Error Control, Parity Generators & Checkers

1.03 Signed Representation, Overflow & Two’s Complement

Overview

Since physical circuits cannot store ”+” or ”-” characters, digital systems dedicate the Most Significant Bit (MSB) of a binary word to represent the sign of a number. The universally adopted system for signed integers in computers is the Signed 2’s Complement System.


1. Signed Binary Representations and Ranges

For an -bit binary word, there are three primary methods used to represent positive and negative integers:

  1. Sign-Magnitude Representation:
    • The MSB is the sign bit (0 for positive, 1 for negative). The remaining bits store the absolute magnitude in true binary.
    • Range:
    • Drawback: Dual representation of zero ( is and is ), complicating arithmetic logic.
  2. Signed 1’s Complement Representation:
    • Positive numbers are identical to Sign-Magnitude. Negative numbers are created by inverting all bits of their positive counterpart.
    • Range:
    • Drawback: Still has dual representation of zero ( and ).
  3. Signed 2’s Complement Representation:
    • Positive numbers are written in true binary. Negative numbers are represented by taking the 2’s complement of the positive value.
    • Range:
    • Benefit: Unique representation of zero (). It also enables subtraction to be handled by standard addition hardware.

1.1 Differences between Signed Binary Representations

FeatureSign-MagnitudeSigned 1’s ComplementSigned 2’s Complement
MSB Function0 = Positive, 1 = Negative0 = Positive, 1 = Negative0 = Positive, 1 = Negative
Negative Number FormulaKeep MSB as 1, copy magnitude.Invert all bits of positive number.Take 2’s complement of positive number.
Range (for bits)
Representation of ZeroTwo representations: (00...0) and (10...0).Two representations: (00...0) and (11...1).One unique representation: 00...0 (always positive).
Hardware Arithmetic ComplexityHigh. Requires separate addition and subtraction circuits.Medium. Requires “End-Around Carry” addition.Low. Single standard adder handles both addition and subtraction.
Mathematical AsymmetrySymmetric range around zero.Symmetric range around zero.Asymmetric. Has one extra negative number (e.g. in 4-bit).

1.2 Comparison Table ( bits)

DecimalSign-MagnitudeSigned 1’s ComplementSigned 2’s Complement
(not defined)
(not defined)(not defined)

2. 8-Bit Signed Arithmetic Tutorial

In an 8-bit computer register, addition and subtraction are handled by standard 8-bit binary addition. Any carry beyond the 8th bit (the sign bit) is discarded.

graph TD
    Start["Setup Operands"] --> trueA["Write +A in 8-bit Binary"]
    Start --> trueB["Write +B in 8-bit Binary"]
    
    trueA --> compA["Find -A (2's Comp of +A)"]
    trueB --> compB["Find -B (2's Comp of +B)"]
    
    compA & compB & trueA & trueB --> Add["Perform 8-bit Addition Only"]
    Add --> Carry{"Carry-out from 8th bit?"}
    Carry -->|Yes| Disc["Discard Carry"]
    Carry -->|No| Check["Check MSB of Sum"]
    Disc --> Check
    
    Check -->|MSB = 0| Pos["Result is Positive. Convert directly to Decimal"]
    Check -->|MSB = 1| Neg["Result is Negative. Take 2's Comp to read magnitude"]

Worked Exam Problem (PYQ 2016, 2017, 2020, 2021, 2025 — 8 to 13 marks)

Question (2021, verbatim): and are integer variables in a computer program with and . Assuming that the computer uses 8-bit two’s complement arithmetic, show how it would compute , , and .

Variants: 2016 and 2017 used ; 2025 asked for only and (08 marks); 2020 made it roll-number dependent — , — so memorising the numbers is useless. Memorise the four-operand setup instead.

Step 0: Pre-Calculation Operand Setup

Convert the absolute magnitudes to 8-bit binary first:

Now write the four required operands:


Case 1: Compute (i.e. )

00011001_2 \quad (+25) \\ + 11010000_2 \quad (-48) \\ \hline 11101001_2 \end{array}$$ - **Evaluation:** No end carry. The MSB is `1`, indicating a **negative** result. - **Find Magnitude:** Take the 2's complement of the sum $11101001_2$: - 1's complement = $00010110_2$ - Add 1 = $00010111_2$ ($23_{10}$) - **Answer:** **$-23_{10}$** (Verifies: $25 - 48 = -23$). --- ### Case 2: Compute $A - B$ (i.e. $25 - (-48) = 25 + 48$) $$\begin{array}{r@{\quad}l} 00011001_2 \quad (+25) \\ + 00110000_2 \quad (+48) \\ \hline 01001001_2 \end{array}$$ - **Evaluation:** No end carry. The MSB is `0`, indicating a **positive** result. - **Find Magnitude:** Convert $01001001_2$ directly to decimal: - $64 + 8 + 1 = 73_{10}$ - **Answer:** **$+73_{10}$** (Verifies: $25 - (-48) = 73$). --- ### Case 3: Compute $B - A$ (i.e. $-48 - 25$) $$\begin{array}{r@{\quad}l} 11010000_2 \quad (-48) \\ + 11100111_2 \quad (-25) \\ \hline (1)\ 10110111_2 \end{array}$$ - **Evaluation:** Carry occurs. Discard the end carry. - The remaining 8-bit sum is $10110111_2$. MSB is `1` $\implies$ **negative** result. - **Find Magnitude:** Take the 2's complement of $10110111_2$: - 1's complement = $01001000_2$ - Add 1 = $01001001_2$ ($73_{10}$) - **Answer:** **$-73_{10}$** (Verifies: $-48 - 25 = -73$). --- ### Case 4: Compute $-A - B$ (i.e. $-25 - (-48) = -25 + 48$) $$\begin{array}{r@{\quad}l} 11100111_2 \quad (-25) \\ + 00110000_2 \quad (+48) \\ \hline (1)\ 00010111_2 \end{array}$$ - **Evaluation:** Carry occurs. Discard the end carry. - The remaining 8-bit sum is $00010111_2$. MSB is `0` $\implies$ **positive** result. - **Find Magnitude:** Convert $00010111_2$ directly to decimal: - $16 + 4 + 2 + 1 = 23_{10}$ - **Answer:** **$+23_{10}$** (Verifies: $-25 + 48 = 23$). $\blacksquare$ --- ## 3. Arithmetic Overflow Conditions When performing signed arithmetic inside an $n$-bit register, the result can exceed the range of representable values: $$\text{Range Limit} = [-2^{n-1} \quad \text{to} \quad +2^{n-1}-1]$$ For an 8-bit system, the valid range is **$-128$ to $+127$**. If the true algebraic sum of two numbers falls outside this range, an **Overflow** occurs, corrupting the sign bit. ### 3.1 The Sign-Bit Check Rule Overflow can **only** occur when adding numbers of the same sign: 1. Adding two positive numbers yields a negative result: $$(+X) + (+Y) = -Z \implies \text{Overflow}$$ 2. Adding two negative numbers yields a positive result: $$(-X) + (-Y) = +Z \implies \text{Overflow}$$ > [!note] Why Adding Opposite Signs Never Causes Overflow > > For an 8-bit signed system: > - Positive range: $[0 \text{ to } +127]$ > - Negative range: $[-1 \text{ to } -128]$ > > Adding any positive $X$ to negative $Y$ is bounded by: > - Maximum possible sum: $(+127) + (-1) = +126$ (safe) > - Minimum possible sum: $(0) + (-128) = -128$ (safe) > > The result is mathematically guaranteed to remain within the $[-128, +127]$ range, making overflow physically impossible. --- ### 3.2 ALU Hardware Detection of Overflow In the Arithmetic Logic Unit (ALU), overflow ($V$) is detected instantly by monitoring the carry bits of the sign-bit position (MSB) using a single XOR gate. ```text Carry-out (Cout) ^ | +----+----+ | XOR Gate| ----> Overflow Flag (V = Cin ⊕ Cout) +----+----+ ^ | Operand A --->| (MSB) Operand B --->| (MSB) | ^ Carry-in (Cin) ``` > [!abstract] Overflow Logic Equation > > > $$\mathbf{V = C_{in} \oplus C_{out}}$$ > > Where: > * $C_{in}$ is the carry-in to the sign-bit position (the carry from column $n-2$ to the MSB column $n-1$). > * $C_{out}$ is the carry-out from the sign-bit position (the final carry beyond the MSB). > * If **$V = 1$**, the sign of the result is incorrect, indicating an **Overflow Error**. --- ### 3.3 Worked Overflow Examples Neither case below can occur in the $A=25,\ B=-48$ problem above (opposite signs are always safe), which is exactly why students never practise it. Both fit in an 8-bit register with range $[-128, +127]$. > [!example] Case 1: Two positives producing a "negative" — $(+100) + (+50)$ > > ```text > 01100100 (+100) > + 00110010 (+50) > ---------- > 10010110 Cout = 0, but carry INTO the MSB column = 1 > ``` > * $V = C_{in} \oplus C_{out} = 1 \oplus 0 = \mathbf{1} \implies$ **Overflow.** > * **Sign-bit check confirms it:** two positive operands produced an MSB of `1`. Read as 2's complement the stored answer is $-106$, but the true sum is $+150$ — and $150 > +127$, so it simply does not fit. > [!example] Case 2: Two negatives producing a "positive" — $(-100) + (-50)$ > > ```text > 10011100 (-100) > + 11001110 (-50) > ---------- > 1 01101010 Cout = 1, but carry INTO the MSB column = 0 > ``` > * $V = C_{in} \oplus C_{out} = 0 \oplus 1 = \mathbf{1} \implies$ **Overflow.** > * Two negative operands produced an MSB of `0`. The stored answer reads $+106$; the true sum is $-150$, below the $-128$ floor. > [!warning] The trap that costs marks > > A carry-out on its own is **not** overflow. In Case 2 a carry appeared and the answer was still wrong; in the $B - A$ computation earlier a carry appeared and the answer was perfectly correct. Overflow is decided by $C_{in} \oplus C_{out}$ — or equivalently by the sign-bit rule — **never** by the carry-out alone. --- > [!question] Past Year Questions (PYQs) > > > | Question (as asked) | Years | Marks | Solved in | > | :--- | :--- | :---: | :--- | > | $A = 25$, $B = -46$, 8-bit two's complement: compute $A+B$, $A-B$, $B-A$, $-A-B$ | 2016, 2017 | 13 | §2 (same method) | > | Same, with $X$, $Y$ derived from your roll number | 2020 | 12 | §2 (same method) | > | $A = 25$, $B = -48$: compute $A+B$, $A-B$, $B-A$, $-A-B$ | 2021 | 13 | §2 Cases 1–4 | > | $A = 25$, $B = -48$: compute $A+B$, $B-A$ only | 2025 | 8 | §2 Cases 1, 3 | > > **Pattern to notice:** this is a near-guaranteed question — five appearances in ten years, always the same four-operand structure. The 2020 roll-number version proves the examiner is testing the *method*, so build the operand table ($A$, $-A$, $B$, $-B$) first, every time, before touching any arithmetic.