Related Concepts: FET biasing concepts | FET biasing - 3 types | FET mosfet biasing

Field Effect Transistors (FET)

1. Definition and Basic Concept

Definition: A Field-Effect Transistor (FET) is a three-terminal semiconductor device where the output current is controlled by an electric field established by an input voltage.

Why “Field-Effect”? The term comes from the ability of the input voltage (applied to the Gate) to create an electric field. This field controls the depletion region width and carrier flow within the device without direct electrical contact between the controlling and controlled terminals.
Unipolar Device: Unlike the BJT (Bipolar), which uses both electrons and holes, the FET is unipolar, depending solely on either electron conduction (n-channel) or hole conduction (p-channel).

Fundamental Difference from BJT

BJT is Current-Controlled: The collector current ( $I_{C}$ ) is a direct function of the base current ( $I_{B}$ ) ( $I_{C} = β I_{B}$ ).
FET is Voltage-Controlled: The drain current ( $I_{D}$ ) is a function of the gate-to-source voltage ( $V_{GS}$ ).
Impedance: FETs typically have a much higher input impedance ( $1 M Ω$ to several hundred $M Ω$ ) compared to BJTs, making them ideal for high-impedance linear amplifier systems.

2. Construction

(Common Exam Question: Sketch the construction of n-channel JFET)

The JFET (Junction Field Effect Transistor) consists of three main terminals:

Source (S): The terminal through which majority carriers enter the bar. Analogous to the Emitter in BJT.
Drain (D): The terminal through which majority carriers leave the bar. Analogous to the Collector in BJT.
Gate (G): The terminal that controls the flow of carriers.

Physical Structure (n-channel JFET):

The major structure is an n-type material forming a channel.
Two smaller layers of p-type material are embedded on the sides and connected to the Gate terminal.
The Drain and Source are connected to the ends of the n-channel via ohmic contacts.
In the absence of bias, two p-n junctions exist, creating depletion regions similar to a diode.

(Note: For p-channel, the materials are reversed: p-type channel and n-type gate).

3. Working Principle

(Common Exam Question: Explain channel formation and pinch-off)

Water Analogy: The Source is the spigot, the Drain is where water exits, and the Gate is the valve controlling flow. The voltage controls the valve constriction.

Operation Steps (n-channel):

No Bias ( $V_{GS} = 0 V, V_{D S} = 0 V$ ): No current flows. Depletion regions are uniform.
Applied Drain Voltage ( $V_{GS} = 0 V, V_{D S} > 0 V$ ): Electrons flow from Source to Drain (conventional current $I_{D}$ flows Drain to Source). As $V_{D S}$ increases, the reverse bias at the Gate-Drain end increases, causing the depletion region to widen more at the top (Drain end) than the bottom.
Pinch-Off: As $V_{D S}$ increases further, the depletion regions expand until they almost touch. This chokes the channel. The voltage where this occurs is the Pinch-off Voltage ( $V_{P}$ ).
- At pinch-off, current does not drop to zero; it saturates at a maximum level called $I_{D SS}$ (Saturation Current).
Applied Gate Voltage ( $V_{GS} < 0 V$ ): Applying a negative voltage to the Gate widens the depletion regions even with small $V_{D S}$ . This constricts the channel sooner.
- Cut-off: If $V_{GS}$ is made sufficiently negative (equal to $V_{P}$ ), the channel closes completely, and $I_{D} = 0 A$ .

Operating Regions:

Ohmic/Linear Region: $V_{D S}$ is small. The JFET acts as a voltage-controlled resistor.
Saturation/Active Region: $V_{D S} > V_{P}$ . Current is constant ( $I_{D} \approx I_{D SS}$ ). Used for amplification.
Cut-off: $V_{GS}$ is very negative (beyond pinch-off). No current flows.
Breakdown: Excessive $V_{D S}$ causes a sudden rise in current, damaging the device.

4. Characteristics

(Common Exam Question: Sketch Transfer and Output characteristics)

Important Parameters:

$I_{D SS}$ : Maximum Drain current (when $V_{GS} = 0 V$ ).
$V_{P}$ (Pinch-off Voltage): The Gate-Source voltage that turns the device off ( $I_{D} = 0$ ).
Transconductance ( $g_{m}$ ): Measures control of Gate voltage over Drain current. Defined as $Δ I_{D} /Δ V_{GS}$ . It is the slope of the transfer curve [Source 2].

Characteristic Curves:

Output (Drain) Characteristics ( $I_{D}$ vs. $V_{D S}$ ):
- Shows $I_{D}$ increasing linearly then saturating.
- Curves move lower as $V_{GS}$ becomes more negative.
Transfer Characteristics ( $I_{D}$ vs. $V_{GS}$ ):
- Unlike BJT (which is linear $β$ ), the relationship in JFET is non-linear (parabolic).
- Defined by Shockley’s Equation: $I_{D} = I_{D SS} (1 - \frac{V _{GS}}{V _{P}})^{2}$ .

5. Types of FET

(Must cover all as per syllabus)

A. Junction FET (JFET)

n-channel: Electrons are carriers. Biased with Positive $V_{D S}$ and Negative $V_{GS}$ .
p-channel: Holes are carriers. Biased with Negative $V_{D S}$ and Positive $V_{GS}$ .

B. Metal-Oxide Semiconductor FET (MOSFET)

Also called IGFET (Insulated Gate FET). Key feature: An insulating $S i O_{2}$ layer separates the Gate from the Channel, resulting in extremely high input impedance.

1. Depletion-Type MOSFET

Construction: Has a physical channel constructed between source and drain.
Operation: Can operate in both Depletion Mode (negative $V_{GS}$ repels electrons, reducing current) and Enhancement Mode (positive $V_{GS}$ attracts electrons, increasing current above $I_{D SS}$ ).
Transfer Curve: Extends into positive $V_{GS}$ region (for n-channel).

2. Enhancement-Type MOSFET

Construction: No physical channel exists initially.
Operation: A positive $V_{GS}$ (for n-channel) is required to attract electrons and “induce” a channel.
Threshold Voltage ( $V_{T}$ ): The minimum $V_{GS}$ required to turn the device ON ( $I_{D} > 0$ ).
Equation: $I_{D} = k (V_{GS} - V_{T})^{2}$ [Source 2].

6. Advantages and Disadvantages

Advantages	Disadvantages
High Input Impedance: $100 M Ω$ (JFET) to $1 0^{14} Ω$ (MOSFET). Minimal loading on sources.	Lower Gain: Voltage gain is generally much less than BJT amplifiers.
Thermal Stability: Less prone to thermal runaway than BJTs.	Bandwidth: Often smaller gain-bandwidth product than BJTs.
Size: Smaller than BJTs, excellent for Integrated Circuits (ICs).	Static Sensitivity: MOSFETs are easily damaged by static electricity due to the thin oxide layer.
Power: CMOS logic consumes very low power.

7. Comparison Tables

FET vs. BJT

(Common Exam Question: 2017, 2016, 2023)

Feature	BJT (Bipolar Junction Transistor)	FET (Field Effect Transistor)
Control	Current Controlled ( $I_{C} = f (I_{B})$ )	Voltage Controlled ( $I_{D} = f (V_{GS})$ )
Carriers	Bipolar (Electrons and Holes)	Unipolar (Electrons OR Holes)
Input Impedance	Low	Very High
Stability	Less temperature stable	More temperature stable
Size	Larger	Smaller (better for ICs)

JFET vs. MOSFET

Feature	JFET	MOSFET
Gate Structure	p-n junction (must be reverse biased)	Insulated Gate ( $S i O_{2}$ layer)
Input Impedance	High ( $1 0^{9} Ω$ )	Ultra High ( $1 0^{12} Ω$ ) [Source 9 Table 8.1]
Operating Mode	Depletion mode only	Depletion and/or Enhancement modes

Depletion vs. Enhancement MOSFET

(Common Exam Question: 2021, 2019, 2016)

Feature	Depletion Type	Enhancement Type
Physical Channel	Physically constructed channel exists.	No physical channel; channel is induced.
Current at $V_{GS} = 0$	Current flows ( $I_{D} = I_{D SS}$ ).	No current ( $I_{D} = 0$ ).
Control Equation	Shockley’s Equation (like JFET).	$I_{D} = k (V_{GS} - V_{T})^{2}$ .

8. Applications

Voltage-Controlled Resistor: JFET resistance $r_{d}$ varies with $V_{GS}$ in the ohmic region. Used in automatic gain control.
Buffer/Isolation Amplifiers: Due to extremely high input impedance (source follower config).
Logic Circuits: CMOS (Complementary MOS) uses paired p-channel and n-channel MOSFETs. Essential for digital computers due to low power consumption.
VMOS/UMOS: Power MOSFETs used for high current/power switching applications.

9. Important Exam Points & PYQ References

Key Definitions (Short Notes):

Pinch-off Voltage ( $V_{P}$ ): The voltage $V_{D S}$ at which the channel is constricted and current saturates ( $V_{GS} = 0$ ); OR the gate voltage that cuts off current ( $V_{GS (o ff)}$ ).
Transconductance ( $g_{m}$ ): The ratio of change in drain current to change in gate voltage [Source 2].
CMOS: Complementary Metal-Oxide Semiconductor. Uses p-type and n-type MOSFETs on the same substrate for high speed/low power logic.

Frequently Asked Theory (from PYQs):

Differences: BJT vs. FET (2023, 2017), Depletion vs. Enhancement MOSFET (2021, 2019).
Reasoning: Why FET has high input impedance (2018) (Answer: Reverse biased junction in JFET; Oxide insulator in MOSFET).
Construction/Operation: Operation of Enhancement MOSFET (2022), Operation of n-channel JFET (2019).
Derivations: Prove $g_{m} = g_{m 0} [1 - V_{GS} / V_{P}]$ (2015).

Formulae for Problems:

JFET/Depletion MOS: $I_{D} = I_{D SS} (1 - V_{GS} / V_{P})^{2}$
Enhancement MOS: $I_{D} = k (V_{GS} - V_{T})^{2}$
Transconductance: $g_{m} = \frac{2 I _{D SS}}{∣ V _{P} ∣} (1 - \frac{V _{GS}}{V _{P}})$

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FET intro