jfet lab report

Related Concepts: JFET Voltage Amplifier | MOSFET Voltage Amplifier | Lab 6 complement power analysis

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Department of Electronic & Communication Engineering Course No.: ECE-1210 Experiment No.: 07 Name of the Experiment: Experiment on Junction Field Effect Transistor

Objectives:

1. To demonstrate and measure the effect of drain voltage ($V_{DS}$) on drain current ($I_D$) with zero gate bias, and determine the drain-source pinch-off voltage ($V_P$).
2. To measure the value of gate-source reverse bias voltage ($V_{GS}$) required to produce pinch-off for a given value of drain-source voltage.

Introduction:

Junction Field Effect Transistors (JFETs) are widely used unipolar devices in electronic circuits. Unlike bipolar junction transistors, JFETs are voltage-controlled devices characterized by a high input impedance. This high impedance is achieved because the gate-source terminals are reverse-biased during normal operation. This experiment studies the $I_D$ vs. $V_{DS}$ characteristics of an N-channel JFET and determines its pinch-off voltage.

Theory:

A conducting JFET exhibits an ohmic region at low drain-source voltages, where the drain current $I_D$ increases linearly with an increase in $V_{DS}$. As $V_{DS}$ increases further, the reverse bias across the junction increases, forming a depletion region that eventually causes the channel to “pinch-off.” Beyond this pinch-off voltage ($V_P$), any further increase in $V_{DS}$ yields no significant increase in $I_D$, and the device operates in the saturation (or constant current) region. Furthermore, applying a reverse gate-source bias ($V_{GS}$) will also reduce the drain current, eventually bringing it to zero.

Circuit Diagram:

• Fig-01: Circuit diagram for measuring $V_{DS}$, $I_D$ for different $V_{DD}$.
• Fig-02: Circuit diagram for finding $V_{GS}$ when $I_D=0$.

Apparatus Required:

Table-01: List of apparatus required for this experiment

SL No.	Apparatus Name	Rating	Quantity
01	DC Power Source	(0 - 30) V	02
02	Transistor (JFET)	2N3819	01
03	Resistors	100 $\Omega$, 1M $\Omega$	02
04	Connecting wires	—	As required

Experimental Data:

Table-02: Table for Pinch-off voltage ($V_{GS}=0V$)

$V_{DS}$ (V)	$I_D$ (mA)
0	0
0.5	4
1	6
1.5	8
2	10
2.5	11
3	11.7
3.5	12
4	12.8
4.5	12.8
5	12.9
6	13.1
6.5	13.1
7	13.1
7.85	13.1
8	13.1

Observed Pinch-off voltage = 6 V.

Table-03: Table for source reverse bias

$V_{GS}$ (V)	$I_D$ (mA)
2	4
2.5	2.5
3	1.3
3.2	1
3.4	0.7
3.5	0.5
3.8	0.2
4	0.1
4.1	0
4.2	0
4.3	0
4.5	0

Observed Saturation $V_P(V_{GS})=-4.1V$.

Result Analysis:

Table-02 shows the relationship between $V_{DS}$ and $I_D$ at zero gate bias. The current initially varies directly with voltage in the ohmic region. Around $V_{DS}=6V$, the current stabilizes at approximately $13.1\text{ mA}$, indicating the JFET has entered the constant current (pinch-off) region. Table-03 illustrates the effect of reverse-biasing the gate. As the reverse bias magnitude increases, the drain current $I_D$ steadily drops. The current reaches zero when a reverse gate-source bias of $4.1V$ is applied, yielding a pinch-off voltage $V_P(V_{GS})$ of $-4.1V$.

Discussion:

In this experiment, the operation of an N-channel JFET was verified. The data clearly demonstrated both the ohmic and saturation regions of the transistor. The pinch-off effects were produced using two different methods (increasing $V_{DS}$ vs. applying reverse $V_{GS}$). A small variation in the gate voltage produced a large variation in drain current, proving the JFET’s capability to operate as an effective amplifier.

Conclusion:

The behavior of a Junction Field Effect Transistor was successfully demonstrated. The experiment confirmed that drain current is controlled by gate voltage and successfully identified the pinch-off voltages under both zero-bias and reverse-bias conditions.

References:

1. Electronic Devices and Circuit Theory — R. Boylestad & L. Nashelsky
2. ECE Laboratory Manual — Dept. of ECE