MOSFET Voltage Amplifier

Related Concepts: FET mosfet biasing

Based on Laboratory Exercise 6: MOSFET Voltage Amplifier from your manual, here is the revision note.

1) Experiment Snapshot

Experiment Title: MOSFET Voltage Amplifier

Objective(s):

Measure DC operating voltages of a MOSFET voltage amplifier.
Demonstrate operation and determine the voltage gain ( $A_{V}$ ).
Measure the phase relationship between gate (input) and drain (output) voltages.

Core Principle / Theory:

Device Type: Uses an N-channel Depletion-mode MOSFET (can operate with zero, positive, or negative gate bias).
Biasing: biased using a voltage divider ( $R 1, R 2$ ) at the gate and a source resistor ( $R 3$ ) for self-bias stability.
Operation: The input signal modulates the channel width, controlling drain current ( $I_{D}$ ).
Characteristics: High input impedance; Voltage gain depends on transconductance ( $g_{m}$ ) and load resistance ( $R_{L}$ ).
Phase: Common Source configuration produces a 180° phase shift (inversion).

Key Formula(s):

Gate-Source Voltage: $V_{GS} = V_{G} - V_{S}$
Voltage Gain: $A_{V} = \frac{e _{o}}{e _{i}}$
Theoretical Gain: $A_{V} = g_{m} \times R_{L}$ (approx)

2) Apparatus Setup

Connection / Block Diagram:

MOSFET (Q1): 40841 (N-Channel). Dual gate connected together.
Input: AF Generator $\to$ Capacitor C1 $\to$ Gate.
Output: Drain $\to$ Capacitor C3 $\to$ Scope/VOM.
Biasing:
- Gate: Voltage divider $R 1 (2.2 M Ω)$ and $R 2 (150 k Ω)$ .
- Source: $R 3 (1 k Ω)$ to ground (bypassed by C2 later).
- Drain: $R 4 (150Ω)$ ? Note: Manual schematic Fig 6-3 shows Load Resistor as R3 (1k) or R4? Text says “Load resistor will be selected…“. Diagram shows Drain connected to $V_{DD}$ via R3 (1k). Let’s follow Fig 6-3: Drain resistor is labeled R3 (1k).
Supply: $V_{DD} = 15 V$ DC.

Precautions:

Static: MOSFETs are sensitive to static electricity; handle carefully.
Wiring: Ensure the dual gates (G1, G2) are connected together as shown in Fig 6-3.

3) Procedure

Part A: DC Operation

Connect circuit (Fig 6-3). $V_{DD} = 15 V$ . Do not connect bypass capacitor C2 yet.
Set AC input to zero.
Measure and record DC voltages with VOM:
- Drain to Ground ( $V_{D}$ )
- Source to Ground ( $V_{S}$ )
- Gate to Ground ( $V_{G}$ )
Calculate $V_{GS}$ ( $V_{G} - V_{S}$ ).

Part B: AC Gain Measurement 5. Set AF Generator to 1kHz Sine Wave. 6. Connect Scope to Gate. Adjust AF Generator for 0.4V pk-pk input ( $e_{i}$ ). 7. Measure output peak-to-peak voltage ( $e_{o}$ ) at the Drain. 8. Calculate Voltage Gain ( $A_{V}$ ). 9. Bypass Capacitor: Connect C2 ( $25 μ F$ ) across Source Resistor R3/R4. 10. Measure new output voltage ( $e_{o}$ ) and calculate new Gain.

Part C: Phase Shift 11. Connect Scope Channel 1 to Input (Gate) and Channel 2 to Output (Drain). 12. Observe the waveforms. Check if the output goes negative when the input goes positive.

4) Data Taken / Measurements

Table Template:

Parameter	Condition	Instrument	Measured Value	Unit
DC Analysis
$V_{D}$ (Drain)	No Signal	VOM	~5 - 12	Vdc
$V_{S}$ (Source)	No Signal	VOM	~1.5	Vdc
$V_{G}$ (Gate)	No Signal	VOM	~1.0	Vdc
$V_{GS}$	Calc: $V_{G} - V_{S}$	-	________	Vdc
AC Analysis
$e_{i}$ (Input)	1kHz	Scope	0.4	$V_{pp}$
$e_{o}$ (Unbypassed)	No C2	Scope	~1.2	$V_{pp}$
$e_{o}$ (Bypassed)	With C2	Scope	~2.3	$V_{pp}$

5) Calculations

DC Bias Check: $V_{GS} = V_{G} - V_{S}$ (Expected: $V_{GS}$ should be approx -0.5V to -1.0V depending on device tolerance).
Voltage Gain (Unbypassed): $A_{V} = \frac{e _{o}}{e _{i}} \approx \frac{1.2}{0.4} = 3$
Voltage Gain (Bypassed): $A_{V} = \frac{e _{o}}{e _{i}} \approx \frac{2.3}{0.4} = 5.75$

6) Results & Outcome

DC Bias: The MOSFET was biased in the depletion mode (normally ON). $V_{G}$ was positive (~1V), but $V_{S}$ was higher (~~1.5V), resulting in a negative $V_{GS}$ (~~ -0.5V).
Gain:
- Without C2: Low gain (~3) due to source resistor degeneration.
- With C2: Higher gain (~6) because AC degeneration is removed.
Phase: Output waveform was 180° out of phase with the input (inverted).

7) Why This Outcome Happens (Reasoning)

Negative $V_{GS}$ : Even though the gate divider provides positive voltage ( $V_{G}$ ), the current flowing through the source resistor creates a voltage drop $V_{S}$ . Since $V_{S} > V_{G}$ , the effective gate-source voltage is negative, biasing the depletion MOSFET correctly.
Gain Increase with C2: The source resistor ( $R_{S}$ ) creates negative feedback (degeneration) which stabilizes DC but reduces AC gain. Adding C2 shorts $R_{S}$ for AC signals, removing the feedback and increasing gain.
Input Impedance: The input impedance is determined by the parallel combination of $R 1$ and $R 2$ (approx $140 k Ω$ ), which is much lower than the intrinsic MOSFET impedance but high enough for standard audio sources.

8) Viva / Lab Test Quick Prep

Q1: Is the 40841 MOSFET Enhancement or Depletion type? A: Depletion type (N-channel). It conducts current with zero gate bias.

Q2: Why do we connect the two gates together? A: To simulate a single-gate MOSFET and utilize the full transconductance.

Q3: What is the purpose of the Source Resistor? A: Self-biasing; it helps stabilize the operating point ( $I_{D}$ ) against temperature and device variations.

Q4: Why does the gain increase when C2 is added? A: C2 acts as a bypass capacitor, preventing AC voltage from developing across the source resistor, thus eliminating degenerative feedback.

Q5: What is the phase relationship between Input and Output? A: 180 degrees out of phase (inverted).

Q6: If $V_{G}$ is 1V and $V_{S}$ is 1.3V, what is $V_{GS}$ ? A: $1 V - 1.3 V = - 0.3 V$ .

Common Mistakes:

Static Damage: Touching the MOSFET pins without grounding yourself (ESD).
Scope Settings: Forgetting to set the scope to AC coupling when measuring small AC signals on top of large DC voltages at the Drain.

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