JFET Voltage Amplifier

Related Concepts: jfet lab report

Based on Laboratory Exercise 3: JFET Voltage Amplifier from your manual, here is the revision note.

1) Experiment Snapshot

Experiment Title: JFET Voltage Amplifier (Common Source)

Objective(s):

Measure DC operating voltages ( $V_{D}, V_{S}, V_{GS}$ ).
Demonstrate operation and determine voltage gain ( $A_{V}$ ).
Measure the phase relationship between the gate (input) and drain (output).

Core Principle / Theory:

Biasing: Uses Self-Bias. The voltage drop across the source resistor ( $V_{S} = I_{D} R_{S}$ ) makes the source positive relative to the gate (which is at 0V), creating the necessary negative $V_{GS}$ to bias the N-channel JFET.
Input Impedance: Extremely high due to the reverse-biased Gate-Source junction.
Voltage Gain: Dependent on transconductance ( $g_{m}$ ) and load resistance ( $R_{L}$ ).
Phase: Common Source configuration produces a 180° phase shift (inversion).

Key Formula(s):

Voltage Gain: $A_{V} = \frac{e _{o}}{e _{i}}$
Theoretical Gain: $A_{V} = g_{m} \times R_{L}$ (approx)
Gate-Source Voltage: $V_{GS} = V_{G} - V_{S}$ (Since $V_{G} \approx 0$ , $V_{GS} \approx - V_{S}$ )

2) Apparatus Setup

Connection / Block Diagram:

Input: AF Generator $\to$ Capacitor C1 $\to$ Gate.
Output: Drain $\to$ Capacitor C2 $\to$ Scope/Load.
Biasing:
- Gate: Connected to Ground via $R 1$ (1 M $Ω$ ).
- Source: Connected to Ground via $R 3$ (1 k $Ω$ ).
- Drain: Connected to $V_{DD}$ via $R 2$ (4.7 k $Ω$ ).
Supply: $V_{DD} = 20 V$ DC.

Precautions:

JFET Handling: Ensure static protection if handling loose components (though less critical than MOSFETs, still good practice).
Wiring: Connect the source bypass capacitor ( $C 2$ in diagram Fig 3-2, but text refers to bypass cap C2 across R3 later) correctly. Note: Manual Fig 3-2 shows C2 as the output coupling cap and C1 as input. Step 3 mentions adding a 25 $μ$ F bypass capacitor.

3) Procedure

Part A: DC Operation

Connect circuit (Fig 3-2). Set $V_{DD} = 20 V$ . Do not connect the bypass capacitor across the source resistor yet.
Set AC input to zero.
Measure and record DC voltages with VOM:
- Drain to Ground ( $V_{D}$ )
- Source to Ground ( $V_{S}$ )
- Gate to Source ( $V_{GS}$ ) directly or calculate ( $V_{G} - V_{S}$ ).

Part B: AC Gain Measurement 4. Set AF Generator to 1000Hz (1kHz) Sine Wave. 5. Adjust input amplitude to get 0.3V pk-pk at the Gate ( $e_{i}$ ). 6. Measure output peak-to-peak voltage ( $e_{o}$ ) at the Drain. 7. Calculate Voltage Gain ( $A_{V}$ ). 8. Bypass Test: Connect a 25 $μ$ F capacitor across the Source Resistor ( $R 3$ ). * Note: Ensure positive terminal of cap faces the Source, negative to ground. 9. Measure new output voltage ( $e_{o}$ ) and calculate gain.

Part C: Phase Shift 10. Connect Scope Channel 1 to Input (Gate) and Channel 2 to Output (Drain). 11. Observe the waveforms to check for phase inversion.

4) Data Taken / Measurements

Table Template:

Parameter	Condition	Instrument	Measured Value	Unit
DC Analysis
$V_{D}$ (Drain)	No Signal	VOM	~10 - 13	Vdc
$V_{S}$ (Source)	No Signal	VOM	~1.8	Vdc
$V_{GS}$	Calc: $0 - V_{S}$	-	~ -1.8	Vdc
AC Analysis
$e_{i}$ (Input)	1kHz	Scope	0.3	$V_{pp}$
$e_{o}$ (Unbypassed)	No Bypass Cap	Scope	~1.0	$V_{pp}$
$e_{o}$ (Bypassed)	With 25 $μ$ F Cap	Scope	~4.0	$V_{pp}$

5) Calculations

DC Bias Check: $V_{GS} = V_{G} - V_{S} \approx 0 V - 1.8 V = - 1.8 V$ (Confirms reverse bias of gate junction).
Voltage Gain (Unbypassed): $A_{V} = \frac{e _{o}}{e _{i}} \approx \frac{1.0}{0.3} = 3.3$
Voltage Gain (Bypassed): $A_{V} = \frac{e _{o}}{e _{i}} \approx \frac{4.0}{0.3} = 13.3$

6) Results & Outcome

DC Bias: The source voltage $V_{S}$ was positive, making $V_{GS}$ negative. This confirms the Self-Biasing action.
Gain:
- Low Gain (Unbypassed): Around 3-4. The source resistor causes degenerative feedback (AC variation in $V_{S}$ opposes input).
- High Gain (Bypassed): Around 13-14. The capacitor shorts AC to ground, removing feedback and maximizing gain.
Phase: The output waveform is 180° out of phase with the input.

7) Why This Outcome Happens (Reasoning)

Self-Bias: Drain current $I_{D}$ flows through $R_{S}$ , creating a voltage drop. Since the Gate resistor $R_{G}$ is connected to ground and draws essentially zero current, $V_{G} = 0 V$ . Thus $V_{GS} = 0 - I_{D} R_{S}$ , providing the necessary negative bias to control the depletion region.
Gain Difference:
- Without Bypass: An increase in $V_{in}$ increases $I_{D}$ , which increases $V_{S}$ . This rise in $V_{S}$ reduces the effective $V_{GS}$ drive ( $V_{GS} = V_{in} - V_{S}$ ), lowering gain.
- With Bypass: The capacitor holds $V_{S}$ steady for AC signals. Full $V_{in}$ is applied across the gate-source junction, resulting in higher $I_{D}$ swing and higher output.
High Input Z: The JFET gate is a reverse-biased diode junction, so it draws negligible current ( $R_{in} \approx R_{G} = 1 M Ω$ ).

8) Viva / Lab Test Quick Prep

Q1: How does “Self-Bias” work in this circuit? A: Current flowing through the source resistor $R_{S}$ creates a voltage drop, making the source positive. Since the gate is at 0V, $V_{GS}$ becomes negative.

Q2: Why is the input impedance of a JFET high? A: Because the Gate-Source junction is always reverse-biased, drawing almost zero gate current.

Q3: What is the effect of adding the source bypass capacitor? A: It increases the AC voltage gain significantly by preventing AC degeneration (feedback) across the source resistor.

Q4: What is the phase relationship between Input and Output? A: 180 degrees out of phase (inverted).

Q5: Is the JFET a voltage-controlled or current-controlled device? A: Voltage-controlled (Voltage at Gate controls Current from Drain to Source).

Q6: What parameter equates to $β$ (current gain) in a BJT but for a FET? A: FETs don’t have current gain $β$ ; their performance is defined by Transconductance ( $g_{m}$ ), which relates input voltage to output current.

Common Mistakes:

Capacitor Polarity: Connecting the bypass capacitor backwards (Positive side must go to Source pin, Negative to Ground).
Measurement: Trying to measure $V_{GS}$ directly without checking if the probe ground clip is isolated (safest to measure $V_{S}$ relative to ground and calculate $V_{GS}$ ).

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