hybrid model numerical methodology

Master Solving Algorithm: BJT $h$-Parameter Problems

This guide outlines a systematic, step-by-step methodology for solving both single-stage and two-stage cascaded Common Emitter (CE) BJT amplifier circuits. It covers both exact and approximate $h$-parameter models using symmetrical impedance notation.

Phase 1: Pre-Calculations (Always Do First)

Before starting the gain or impedance formulas, analyze the schematic to determine the effective AC resistances on the input and output boundaries.

Step 1.1: Determine the Effective AC Load Resistance ($R_L^{\prime }$)

In the AC equivalent domain, DC supply voltage rails ($V_{CC}$) and bypass capacitors act as short circuits to AC ground. Therefore, the internal collector resistor ($R_C$) and the external load resistor ($R_L$) sit in parallel.

• Formula:

  $R_L^{\prime }=R_C\parallel R_L=\frac{R_C\cdot R_L}{R_C+R_L}$

• Note: If there is no external load resistor $R_L$ connected to the output, then $R_L^{\prime }=R_C$.

Step 1.2: Determine the Equivalent Base Biasing Resistance ($R_B$)

The voltage-divider biasing resistors ($R_1$ and $R_2$) are connected in parallel with respect to the AC signal path.

• Formula:

  $R_B=R_1\parallel R_2=\frac{R_1\cdot R_2}{R_1+R_2}$

Phase 2: Single-Stage Solution Sequence

If the circuit contains only a single transistor stage, execute the calculations in this exact, progressive order:

[AC Load (R_L')] ──> [Current Gain (A_I)] ──> [Transistor Input Impedance (Z_i)]
                           │
                           └──> [Voltage Gain (A_V)] ──> [System Gain (A_vs)]

Step 2.1: Transistor Current Gain ($A_I$)

Always start here. You cannot calculate input impedance or voltage gain without first finding the current gain.

• Exact Model:

  $A_I=\frac{-h_{fe}}{1+h_{oe}{R}_L^{\prime }}$

• Approximate Model: (Use if $h_{oe}$ is not specified or is negligible)

  $A_I\approx -h_{fe}$

Step 2.2: Transistor Internal Input Impedance ($Z_i$)

This is the impedance looking directly into the physical Base terminal of the transistor.

• Exact Model:

  $Z_i=h_{ie}+h_{re}{A}_I{R}_L^{\prime }$

• Approximate Model: (Use if $h_{re}$ is not specified or is negligible)

  $Z_i\approx h_{ie}$

Step 2.3: Transistor Internal Voltage Gain ($A_V$)

This is the voltage gain from the transistor’s Base terminal to its Collector terminal ($V_o/V_i$).

• Formula:

  $A_V=\frac{A_I{R}_L^{\prime }}{Z_i}$

Step 2.4: Overall Stage Input Impedance ($Z_{in}$)

The signal source sees the biasing network in parallel with the transistor’s base terminal ($Z_i$).

• Formula:

  $Z_{in}=R_B\parallel Z_i=\frac{R_B\cdot Z_i}{R_B+Z_i}$

Step 2.5: Overall System Voltage Gain ($A_{vs}$)

This accounts for the signal attenuation across the internal source resistance ($R_S$) using an input voltage divider.

• Formula:

  $A_{vs}=\frac{V_o}{V_s}=A_V\cdot \left(\frac{Z_{in}}{Z_{in}+R_S}\right)$

Step 2.6: Overall System Current Gain ($A_{is}$)

This is the ratio of output load current to source generator current ($I_L/I_s$).

• Formula:

  $A_{is}=A_{vs}\cdot \left(\frac{R_S+Z_{in}}{R_L}\right)$

Step 2.7: Amplifier Stage Output Impedance ($R_o$ or $Z_{out}$)

1. Find the effective AC source resistance seen by the base:

   $R_s^{\prime }=R_S\parallel R_B$

2. Calculate the transistor’s internal output admittance ($Y_o$):

   $Y_o=h_{oe}-\frac{h_{fe}{h}_{re}}{h_{ie}+R_s^{\prime }}$

3. Find the overall stage output resistance by placing the transistor output impedance ($Z_o=1/Y_o$) in parallel with the collector resistor:

   $R_o=Z_o\parallel R_C=\frac{1}{Y_o}\parallel R_C$

• Approximate Model Simplification: If $h_{oe}=0$ and $h_{re}=0$, then $Z_o\approx \infty$, which simplifies the stage output impedance to:

  $R_o\approx R_C$

Phase 3: Multi-Stage (Cascade) Solution Sequence

The Golden Rule of Cascade Analysis: Always analyze backwards, beginning with the final output stage and working toward the input stage.

[Stage 2 Output Load] ──> [Analyze Stage 2 (A_I2, Z_i2)] ──> [Calculate Z_in2]
                                                                   │
[Calculate Stage 1 Overall Parameters] <── [Analyze Stage 1 (R_L1')] ┘

Step 3.1: Analyze the Second Stage (Stage 2)

Treat the final stage exactly like a standalone single-stage amplifier.

1. Find the final AC load:

   $R_{L2}^{\prime }=R_{C2}\parallel R_{L2}$

2. Calculate Stage 2 current gain:

   $A_{I2}=\frac{-h_{fe2}}{1+h_{oe2}{R}_{L2}^{\prime }}$

3. Calculate Stage 2 internal input impedance:

   $Z_{i2}=h_{ie2}+h_{re2}{A}_{I2}{R}_{L2}^{\prime }$

4. Calculate Stage 2 internal voltage gain:

   $A_{V2}=\frac{A_{I2}{R}_{L2}^{\prime }}{Z_{i2}}$

5. Calculate Stage 2 overall stage input impedance:

   $Z_{in2}=R_{B2}\parallel Z_{i2}$

Step 3.2: Analyze the First Stage (Stage 1)

Stage 1 is loaded down by the overall input impedance of Stage 2.

1. Calculate the effective AC load of Stage 1 ($R_{L1}^{\prime }$):

   The load seen by the collector of $Q_1$ is the parallel combination of its own collector resistor and the total input impedance of Stage 2.

   $R_{L1}^{\prime }=R_{C1}\parallel Z_{in2}=R_{C1}\parallel R_{B2}\parallel Z_{i2}$

2. Calculate Stage 1 current gain:

   $A_{I1}=\frac{-h_{fe1}}{1+h_{oe1}{R}_{L1}^{\prime }}$

3. Calculate Stage 1 internal input impedance:

   $Z_{i1}=h_{ie1}+h_{re1}{A}_{I1}{R}_{L1}^{\prime }$

4. Calculate Stage 1 internal voltage gain:

   $A_{V1}=\frac{A_{I1}{R}_{L1}^{\prime }}{Z_{i1}}$

5. Calculate Stage 1 overall stage input impedance:

   $Z_{in1}=R_{B1}\parallel Z_{i1}$

Step 3.3: Calculate Overall Cascade System Parameters

Once both stages have been analyzed individually, link them together to obtain the full system metrics.

1. Overall Transistor Voltage Gain ($A_V$):

   $A_V=A_{V1}\cdot A_{V2}$

2. Overall Cascade System Input Impedance ($Z_{in}$):

   This is simply the total input impedance of the very first stage:

   $Z_{in}=Z_{in1}$

3. Overall System Output Impedance ($R_o^{\prime }$ or $Z_{out}$):

   This is the output impedance of the second stage looking back from the load terminal:

   $R_o^{\prime }=Z_{o2}\parallel R_{C2}$

4. Overall System Voltage Gain with Source ($A_{Vs}$):

   $A_{Vs}=\frac{V_o}{V_s}=A_V\cdot \left(\frac{Z_{in1}}{Z_{in1}+R_S}\right)$

5. Overall System Current Gain ($A_{Is}$):

   $A_{Is}=\frac{I_L}{I_s}=A_{Vs}\cdot \left(\frac{R_S+Z_{in1}}{R_L}\right)$

Phase 4: Demystifying $R$ (Resistance) vs. $Z$ (Impedance)

During exam pressure, keeping $R$ and $Z$ straight can prevent easily avoided formula errors. Here is the physical and conceptual breakdown of the notations.

4.1. Why are they numerically identical in these problems?

• Physical Impedance ($Z$): Consists of a real part (Resistance, $R$) and an imaginary part (Reactance, $X$): $Z=R+jX$.

• The Midband Frequency Assumption: In small-signal analysis, we assume we are in the midband frequency range where:

  1. Coupling and bypass capacitors act as perfect AC shorts ($X_C\approx 0$).

  2. Transistor parasitic internal capacitors act as perfect AC opens ($X_C\approx \infty$).

• Because there are no imaginary reactive elements ($X=0$) left in our AC equivalent model, impedance and resistance are numerically identical ($Z=R$). Both are purely real numbers measured in Ohms ($\Omega$).

4.2. Understanding the Input Boundaries ($Z_i$ vs. $Z_{in}$)

The distinction between these two variables lies in where you are standing when you look into the circuit:

                  ┌───────── Overall Stage Input Impedance (Zin) ────────┐
                  │                                                      │
                  ▼                                                      │
Source (Vs) ───[ Rs ]───┬──────────────┬─────────────── Base (B)         │
                        │              │               │                 │
                        ▼              ▼               ▼                 │
                       [R1]           [R2]       ┌───────────┐           │
                        │              │         │           │           │
                        ▼              ▼         │Transistor │           │
                       GND            GND        │           │           │
                                                 └───────────┘           │
                                                 ▲                       │
                                                 │                       │
                                                 └─ Transistor-only (Zi) ┘

1. Transistor-only Input Impedance ($Z_i$):

   • Where you stand: Directly at the Base terminal of the transistor.

   • What you see: The internal resistance of the emitter-base junction ($h_{ie}$) modified by internal feedback ($h_{re}{A}_I{R}_L^{\prime }$).

   • Scope: Excludes the biasing resistors ($R_1,R_2$) and source resistor ($R_S$).

2. Overall Stage Input Impedance ($Z_{in}$):

   • Where you stand: Right after the source resistor $R_S$.

   • What you see: The parallel combination of the biasing network and the transistor’s base: $R_B\parallel Z_i$.

   • Scope: Excludes only $R_S$.

4.3. Understanding the Output Boundaries ($Z_o$ vs. $R_o$)

The distinction on the output boundary separates internal active semiconductor parameters from external layout designs:

                            Collector (C) ─── Output Terminal (Vo)
                            │                 │
                            ▼                 ▼
                     ┌───────────┐           [Rc]
                     │           │            │
                     │Transistor │            ▼
                     │ (Yo = 1/Zo)            GND
                     └───────────┘            
                     ▲                        ▲
                     │                        │
                     └─ Transistor-only (Zo) ─┴─ Overall Stage (Ro)

1. Transistor-only Output Impedance ($Z_o$):

   • Where you stand: Standing inside the collector terminal looking backward into the active transistor channel.

   • What you see: The reciprocal of the output admittance ($Z_o=1/Y_o$).

   • Scope: Excludes the collector bias resistor $R_C$ and the load resistor $R_L$.

2. Overall Stage Output Impedance ($R_o$ or $Z_{out}$):

   • Where you stand: Standing at the output terminal where the external load ($R_L$) would connect, looking back toward the amplifier.

   • What you see: The parallel combination of the transistor’s channel impedance $Z_o$ and the collector resistor $R_C$: $R_o=Z_o\parallel R_C$.

   • Scope: Excludes the external load $R_L$.

Practical Troubleshooting & Formula Selection Rules

Scenario	Decision Rule	Action
All 4 $h$-parameters are provided ($h_{ie},h_{fe},h_{re},h_{oe}$)	Use the Exact Model	Implement the full formulas for $A_I$, $Z_i$, and $Y_o$. Do not neglect terms.
Only $h_{ie}$ and $h_{fe}$ are provided (or $h_{re}$, $h_{oe}$ are set to zero)	Use the Approximate Model	Set $Z_i\approx h_{ie}$, $A_I\approx -h_{fe}$, and $R_o\approx R_C$.
An emitter resistor $R_E$ is present with NO bypass capacitor	Modified Equations Required	Do not use basic CE formulas. You must derive or use equations with feedback ($Z_i\approx h_{ie}+(1+h_{fe})R_E$).
A bypass capacitor is connected across $R_E$	Treat as standard CE	$R_E$ is shorted to ground at AC frequencies. Use the standard sequences above.