3.04 State-Space Modeling of Block Diagrams and Signal Flow

Related Concepts: 3.01 Introduction to State-Space & Phase-Variable Formulations | 3.02 State-Space Modeling of Transfer Functions (Canonic Forms) | 3.03 State-Space Modeling of Electrical Circuits

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3.04 State-Space Modeling of Block Diagrams & Signal Flow Graphs

Core Idea

Operational block diagrams and signal flow graphs (SFGs) are graphical representations of a system’s mathematical relationships. By assigning state variables to the outputs of integrators (in continuous-time systems) or unit delays (in discrete-time systems), we can systematically extract the coupled first-order matrix state equations ($\mathbf{A},\mathbf{B},\mathbf{C},\mathbf{D}$) directly from the graphical signal paths.

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1. State-Variable Assignment Rules for Graphical Systems

To systematically formulate state equations from any block diagram or signal flow graph, we apply two rigid assignment rules depending on the system domain:

Rule 1: Continuous-Time (CT) Systems (Integrators)

The state variables represent the output signals of the integrator blocks {integrators accumulate signals over time}.

• If an integrator block has output $x_k(t)$, then its input must be the first derivative of that state: $\text{Output of Integrator }k=x_k(t)⟹\text{Input of Integrator }k={\dot{x}}_k(t)$
• For a system of order $n$, there will be exactly $n$ cascaded or parallel integrator blocks ($1/s$ in the s-domain), yielding $n$ state variables.

Rule 2: Discrete-Time (DT) Systems (Unit Delays)

The state variables represent the output signals of the unit delay blocks {delays hold discrete samples for one interval}.

• If a unit delay block ($z^{-1}$) has output $x_k[n]$, then its input must be the next advanced sample state: $\text{Output of Delay Block }k=x_k[n]⟹\text{Input of Delay Block }k=x_k[n+1]$
• For a discrete system of order $n$, there will be exactly $n$ delay elements, yielding $n$ discrete state variables.

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2. Rigorous 5-Step Graphical-to-Matrix Algorithm

Follow this mechanical checklist to convert any operational flowchart into state-space matrix format:

graph TD
    A[Step 1: Label Outputs of Integrators/Delays as x_i] --> B[Step 2: Label Inputs of Integrators/Delays as dx_i or x_i_plus_1]
    B --> C[Step 3: Write Equations for Adder Nodes in terms of x_i and u]
    C --> D[Step 4: Express System Output y in terms of x_i and u]
    D --> E[Step 5: Assemble Vector-Matrix Equations A, B, C, D]

1. Step 1: Identify all integrator blocks ($1/s$) or delay blocks ($z^{-1}$). Label their outputs as state variables $x_1,x_2,\dots ,x_n$.
2. Step 2: Label the inputs to these blocks as ${\dot{x}}_1,{\dot{x}}_2,\dots ,{\dot{x}}_n$ (for CT) or $x_1[n+1],x_2[n+1],\dots ,x_n[n+1]$ (for DT).
3. Step 3: Systematically write algebraic equations for each adder node {summation points} in the diagram. Express the derivative/advanced states (${\dot{x}}_i$ or $x_i[n+1]$) strictly as a linear combination of the state variables $x_j$ and the external inputs $u$.
4. Step 4: Write the output equation by expressing $y(t)$ or $y[n]$ strictly in terms of the state variables $x_j$ and input $u$.
5. Step 5: Group coefficients and assemble into the canonical matrix format: \text{State Equation:} & \quad \mathbf{\dot{X}} = \mathbf{A}\mathbf{X} + \mathbf{B}\mathbf{U} \\ \text{Output Equation:} & \quad \mathbf{Y} = \mathbf{C}\mathbf{X} + \mathbf{D}\mathbf{U} \end{aligned}$$

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3. Continuous-Time (CT) Block Diagram Modeling

Consider a continuous-time system containing three integrators. We want to extract the state-space representation directly from its hardware block wiring.

3.1 Worked Numerical: Multi-Feedback Integrator Diagram

Question: Obtain the state model $(\mathbf{A},\mathbf{B},\mathbf{C},\mathbf{D})$ of the continuous-time block diagram represented below:

[DIAGRAM: Continuous 3-integrator block diagram. Input u(t) enters an adder on the left. The output of this adder goes into Integrator 1. The output of Integrator 1 is state x3(t), which feeds into Integrator 2. The output of Integrator 2 is state x2(t), which feeds into Integrator 3. The output of Integrator 3 is state x1(t). Feedback gains of -5, -4, and -2 are taken from state outputs x1(t), x2(t), and x3(t) respectively, and routed back to the main input adder. The output y(t) is a linear sum of x1(t) and x2(t) - source: Azmat Sir Slide 15]

Step-by-Step Solution:

• Step 1: Assign States Let the outputs of the three integrators be assigned as: $x_1(t),x_2(t),x_3(t)$

• Step 2: Assign State Derivatives The inputs to the integrators are: ${\dot{x}}_1(t),{\dot{x}}_2(t),{\dot{x}}_3(t)$

• Step 3: Establish Integrator Connections From the cascading connections:

  \dot{x}_1(t) &= x_2(t) \\ \dot{x}_2(t) &= x_3(t) \end{aligned}$$

• Step 4: Write Main Adder Equation The input to the first integrator is ${\dot{x}}_3(t)$, which is the output of the main feedback adder node. Let us trace the signals entering this adder: ${\dot{x}}_3(t)=-5x_1(t)-4x_2(t)-2x_3(t)+u(t)$

• Step 5: Write Output Equation The system output $y(t)$ is the sum of $x_1(t)$ and $x_2(t)$: $y(t)=x_1(t)+x_2(t)$

• Step 6: Assemble State-Space Matrices $\left[\begin{array}{c}{\dot{x}}_1(t)\\ {\dot{x}}_2(t)\\ {\dot{x}}_3(t)\end{array}\right]=\left[\begin{array}{ccc}0& 1& 0\\ 0& 0& 1\\ -5& -4& -2\end{array}\right]\left[\begin{array}{c}{x}_1(t)\\ x_2(t)\\ x_3(t)\end{array}\right]+\left[\begin{array}{c}0\\ 0\\ 1\end{array}\right]u(t)$ $y(t)=\left[\begin{array}{ccc}1& 1& 0\end{array}\right]\left[\begin{array}{c}{x}_1(t)\\ x_2(t)\\ x_3(t)\end{array}\right]+\left[\begin{array}{c}0\end{array}\right]u(t)$

  Thus, the continuous-time state matrices are: $\mathbf{A}=\left[\begin{array}{ccc}0& 1& 0\\ 0& 0& 1\\ -5& -4& -2\end{array}\right],\mathbf{B}=\left[\begin{array}{c}0\\ 0\\ 1\end{array}\right],\mathbf{C}=\left[\begin{array}{ccc}1& 1& 0\end{array}\right],\mathbf{D}=\left[\begin{array}{c}0\end{array}\right]$

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4. Discrete-Time (DT) Block Diagram Modeling

Discrete-time diagrams utilize unit delays ($z^{-1}$). The mathematical extraction requires careful tracking of step indices.

4.1 Worked Numerical: Unit Delay Network [PYQ 2016]

Question: Find the state-space description $(\mathbf{A},\mathbf{B},\mathbf{C},\mathbf{D})$ corresponding to the system depicted below by choosing the state variables to be the outputs of the unit delays:

[DIAGRAM: Discrete-time realization block diagram containing two delay blocks (z^-1). Node labels: Input u[n] enters on the left, feeding into a top-path adder and a bottom-path adder. Delay Block 1 has output state x1[n], and Delay Block 2 has output state x2[n]. Tracing feedback path loops: the input to Delay 1 (x1[n+1]) is fed by u[n] + 1/3 x2[n]. The input to Delay 2 (x2[n+1]) is fed by the output of a multiplier (4/3) from x2[n] + x1[n] + u[n]. The output y[n] is tapped from the final right-side adder node - source: KUET 2016 Question 4a]

Step-by-Step Solution:

1. Assign State Variables: Let the outputs of the delay blocks be the states: $\mathbf{X}[n]=\left[\begin{array}{c}{x}_1[n]\\ x_2[n]\end{array}\right]$

2. Establish Advanced State Equations: Tracing the signals at the inputs of the delays ($x_i[n+1]$): $x_1[n+1]=\frac{1}{3}{x}_2[n]+u[n]$ $x_2[n+1]=x_1[n]+\frac{4}{3}{x}_2[n]+u[n]$

3. Establish Output Equation: Tracing the output path $y[n]$ from the final right-side adder node: $y[n]=x_1[n]+\frac{4}{3}{x}_2[n]+u[n]$

4. Formulate Coupled Matrices: $\left[\begin{array}{c}{x}_1[n+1]\\ x_2[n+1]\end{array}\right]=\left[\begin{array}{cc}0& \frac{1}{3}\\ 1& \frac{4}{3}\end{array}\right]\left[\begin{array}{c}{x}_1[n]\\ x_2[n]\end{array}\right]+\left[\begin{array}{c}1\\ 1\end{array}\right]u[n]$ $y[n]=\left[\begin{array}{cc}1& \frac{4}{3}\end{array}\right]\left[\begin{array}{c}{x}_1[n]\\ x_2[n]\end{array}\right]+\left[\begin{array}{c}1\end{array}\right]u[n]$

   Thus, the final discrete state-space matrices are: $\mathbf{A}=\left[\begin{array}{cc}0& \frac{1}{3}\\ 1& \frac{4}{3}\end{array}\right],\mathbf{B}=\left[\begin{array}{c}1\\ 1\end{array}\right],\mathbf{C}=\left[\begin{array}{cc}1& \frac{4}{3}\end{array}\right],\mathbf{D}=\left[\begin{array}{c}1\end{array}\right]$

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5. Signal Flow Graph (SFG) State-Space Formulations

A Signal Flow Graph (SFG) is a simplified directed graph where nodes represent variables and branches represent gains. It is mathematically equivalent to block diagrams.

5.1 The SFG State Extraction Rule

• Identify all branch transmittance terms that contain the integrator factor $s^{-1}$ (or delay factor $z^{-1}$).
• The State Node Rule: The output node of every branch with transmittance $s^{-1}$ is designated as a state variable $x_i(t)$. The input node to that same branch represents the derivative of that state, ${\dot{x}}_i(t)$.

               \dot{x}_i(t)     1/s      x_i(t)
              o-------------( Integrator )------------->o

• Write nodal equations for all derivative nodes (${\dot{x}}_i$) by summing all incoming branch signals entering that specific node.

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6. Common Mistakes That Cost Marks

The Integrator Output-Input Swapping Trap

Never swap the input and output variables of the integrator! The output of the integrator block is the state $x_i(t)$, and the input is ${\dot{x}}_i(t)$. If you mistakenly write the input as $x_i(t)$ and output as ${\dot{x}}_i(t)$, your derivative equations will involve unwanted integral calculus, completely violating the algebraic first-order state format.

The Direct Feedforward Path ($\mathbf{D}$) Oversight

Always verify if there is a direct feedforward path bypassing the delay/integrator chains directly from the input terminal $u(t)$ to the output terminal $y(t)$. If such a path exists (for example, a gain branch running from start to finish), your direct transmission matrix $\mathbf{D}$ is non-zero ($\mathbf{D}\ne 0$). Forgetting to include this feedforward term in your output equation yields a major structural grading deduction.

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7. PYQ Bank — Verbatim Questions & Answer Plans

7.1 PYQ 2016 Question 4a [12 Marks]

Question: Find the state variable description corresponding to the system depicted in Fig. 4(a) by choosing the state variables to be the outputs of the unit delays.

• Answer Plan: Follow the step-by-step discrete mathematical derivation provided in Section 4.1. Clearly label the state variables $x_1[n]$ and $x_2[n]$ at the delay outputs, trace the inputs $x_1[n+1]$ and $x_2[n+1]$, formulate the node state equations, write the output equation, and present the final matrices ($\mathbf{A},\mathbf{B},\mathbf{C},\mathbf{D}$) with their respective dimensions to secure all 12 marks.

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8. Self-Check Before Moving On

• Can you define state-variable assignment rules for continuous integrators and discrete unit delays?
• Do you know how to write algebraic equations for adder nodes by summing incoming branch signals?
• Have you mastered the 5-step graphical-to-matrix mapping algorithm?
• Can you identify non-zero $\mathbf{D}$ matrices caused by direct input-output feedforward branches?

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Source: (k.Deergha Rao) signals and systems.pdf (Chapter 8), ECE-2107_STATE_SPACE_ANALYSIS.pdf, Azmat Sir-2309008.pdf (Class Lecture Slides).