2.05 Block-Diagram Representations & System Interconnections

[!abstract] Block-Diagram Realization A graphical representation mapping the algebraic relations of linear constant-coefficient differential equations (LCCDEs) or difference equations into elementary physical hardware blocks. It serves as the physical bridge between abstract time-domain equations and practical analog circuit computer simulations {using operational amplifiers} or digital signal processing (DSP) hardware chips {using registers and adders}.

1. Basic Building Blocks of LTI Systems

Before drawing system architectures, we must master the standard graphical symbols. These blocks are the elementary operations we perform on signals in analog and digital domains.

1.1 Continuous-Time (CT) Realization Blocks

Continuous-time systems are physically built using operational amplifiers (op-amps), resistors, and capacitors. The three fundamental building blocks are:

Element	Algebraic Relation	Graphical representation (ASCII)	Physical Implementation
CT Integrator	$y (t) = \int_{- \infty}^{t} x (τ) d τ$	`x(t) ----> [ 1/s ] ----> y(t)`	Op-amp integrator circuit with capacitor feedback
CT Adder	$y (t) = x_{1} (t) + x_{2} (t)$	`x1(t) ----\` `( + ) ----> y(t)` `x2(t) ----/`	Op-amp summing amplifier circuit
CT Multiplier	$y (t) = c \cdot x (t)$	`x(t) ----> ( c ) ----> y(t)`	Op-amp inverting/non-inverting amplifier with gain $c$

1.2 Discrete-Time (DT) Realization Blocks

Discrete-time systems do not use capacitors or integration. Instead, they operate on digital clock cycles using registers, logic adders, and multipliers:

Element	Algebraic Relation	Graphical representation (ASCII)	Physical Implementation
DT Unit Delay	$y [n] = x [n - 1]$	`x[n] ----> [ z^-1 ] ----> y[n]`	Digital register / flip-flop clocked delay element
DT Adder	$y [n] = x_{1} [n] + x_{2} [n]$	`x1[n] ----\` `( + ) ----> y[n]` `x2[n] ----/`	Logic adder circuit
DT Multiplier	$y [n] = c \cdot x [n]$	`x[n] ----> ( c ) ----> y[n]`	Digital hardware multiplier circuit

2. Realization of Continuous-Time Systems (LCCDEs)

For a general $N$ -th order continuous-time linear constant-coefficient differential equation: $\sum_{n = 0}^{N} a_{n} \frac{d ^{n} y ( t )}{d t ^{n}} = \sum_{m = 0}^{M} b_{m} \frac{d ^{m} x ( t )}{d t ^{m}}$

To draw the block diagram, we must solve for the highest-order derivative of the output, $\frac{d ^{N} y ( t )}{d t ^{N}}$ , by isolating it on the left-hand side: $\frac{d ^{N} y ( t )}{d t ^{N}} = \frac{1}{a _{0}} [\sum_{m = 0}^{M} b_{m} \frac{d ^{m} x ( t )}{d t ^{m}} - \sum_{n = 1}^{N} a_{n} \frac{d ^{N - n} y ( t )}{d t ^{N - n}}]$

The $a_{0}$ Division Trap (Rabiul Sir's Lab Warning)

Always check if the coefficient of the highest-order derivative of the output, $a_{0}$ , is equal to 1. If $a_{0} \neq = 1$ , you must divide every single coefficient in the equation by $a_{0}$ before drawing! Forgetting this division is the #1 source of lost marks in both the exam and the lab [Rabiul Sir Class Note].

2.1 Direct Form I Realization (Non-Canonic)

Direct Form I represents a literal translation of the differential equation. It realizes the input operations (feedforward zeros) first, followed by the output operations (feedback poles) in series:

Input x(t) ---> [ Feedforward zeros (System 1) ] ---> [ Feedback poles (System 2) ] ---> Output y(t)

Characteristics: It keeps the input and output scaling operations completely independent.
Drawback: For an $N$ -th order system, it requires $M + N$ integrators, which is hardware-inefficient.

2.2 Direct Form II Realization (Canonic)

Direct Form II is obtained by reversing the order of the cascaded subsystems: realizing the feedback poles first, followed by the feedforward zeros:

Input x(t) ---> [ Feedback poles (System 2) ] ---> [ Feedforward zeros (System 1) ] ---> Output y(t)

By swapping the cascade order, the intermediate state nodes are identical. We can merge the parallel branches, sharing the exact same integrators down the center column of the diagram!

Canonic Property: A system realization is called canonic if it uses the absolute minimum number of integrators/delays possible, which is exactly equal to the system order, $N$ [Textbook Sec 2.6].
Hardware Savings: Direct Form II cuts the required number of integrators exactly in half!

3. Realization of Discrete-Time Systems (Difference Equations)

In the discrete-time domain, the difference equation relates input and output sequences: $\sum_{n = 0}^{N} a_{n} y [n - n] = \sum_{m = 0}^{M} b_{m} x [n - m]$

Assuming $a_{0} = 1$ , we solve for the present output $y [n]$ : $y [n] = \sum_{m = 0}^{M} b_{m} x [n - m] - \sum_{n = 1}^{N} a_{n} y [n - n]$

3.1 Discrete Direct Form I

Realizes the delay lines for the input sequence $x [n]$ and output sequence $y [n]$ on separate delay paths.

3.2 Discrete Direct Form II (Canonic)

Creates a single center delay line using an intermediate digital state sequence $w [n]$ : $w [n] = x [n] - \sum_{n = 1}^{N} a_{n} w [n - n]$ $y [n] = \sum_{m = 0}^{M} b_{m} w [n - m]$

Structure:
- Left-hand side (Feedback): Feeds back delayed states of $w [n]$ multiplied by negated coefficients $- a_{n}$ into the main summing junction.
- Right-hand side (Feedforward): Feeds forward delayed states of $w [n]$ multiplied by $b_{m}$ coefficients into the output summing junction.

4. Step-by-Step Solved Numericals

📝 Numerical 1: Continuous-Time Realization (KUET 2024, 2022)

Question: Obtain the block-diagram representation of a continuous-time system described by: $\frac{d ^{2} y ( t )}{d t ^{2}} + 2 \frac{d y ( t )}{d t} + y (t) = \frac{d ^{2} x ( t )}{d t ^{2}} - \frac{d x ( t )}{d t} - 6 x (t)$

Step-by-Step Solution:

Step 1: Check $a_{0}$ and identify coefficients The highest derivative coefficient is $a_{0} = 1$ . The system order is $N = 2$ .

Output coefficients: $a_{1} = 2$ , $a_{2} = 1$ .
Input coefficients: $b_{0} = 1$ , $b_{1} = - 1$ , $b_{2} = - 6$ .

Step 2: Set up the intermediate feedback equation Define the intermediate state variable $w (t)$ in the s-domain or time-domain: $\overset{w}{¨} (t) = x (t) - 2 \overset{w}{˙} (t) - w (t)$

Step 3: Set up the output feedforward equation $y (t) = \overset{w}{¨} (t) - \overset{w}{˙} (t) - 6 w (t)$

Step 4: Draw the Direct Form II Block Diagram We cascade two CT integrators down the center to generate $\overset{w}{˙} (t)$ from $\overset{w}{¨} (t)$ , and $w (t)$ from $\overset{w}{˙} (t)$ .

               Input x(t)
                   |
                   v
               +-------+
       +-----> |   +   | <----------------+
       |       +-------+                  |
       |           | \                    |
       |           |  \                   |
       |           v   \ ( b0 = 1 )       |
       |      ddot w(t) \                 |
       |           |     v                |
       |        [ 1/s ] --->( + )         |
       |           |         ^            |
       |           v         |            | ( -a2 = -1 )
       | ( -a1 = -2 )        |            |
       +<----( -2 )+--dot w(t)            |
       |           |         |            |
       |           |   ( b1 = -1 )        |
       |           v         |            |
       |        [ 1/s ] ---->+            |
       |           |         |            |
       |           v         v            |
       +<----( -1 )+--- w(t)              |
                   |                      |
                   +------>( -6 )-------->+-----> Output y(t)
                         ( b2 = -6 )

📝 Numerical 2: Discrete-Time Realization with “Trap” Coefficients (KUET 2025, 2019)

Question: Draw the canonic Direct Form II realization for the system described by the difference equation: $y [n] + \frac{1}{3} y [n - 1] + \frac{1}{5} y [n - 3] = x [n - 1]$

Step-by-Step Solution:

Step 1: Identify coefficients and system order The highest delay is 3, so system order is $N = 3$ . This requires exactly 3 delay elements ( $z^{- 1}$ ) for canonic realization.

Output coefficients: $a_{0} = 1$ , $a_{1} = 1/3$ , $a_{2} = 0$ , $a_{3} = 1/5$ . (Note: $a_{2} = 0$ is a trap!)
Input coefficients: $b_{0} = 0$ , $b_{1} = 1$ , $b_{2} = 0$ , $b_{3} = 0$ . (Note: Only $b_{1}$ is non-zero, another trap!)

Step 2: Formulate the canonic node equations $w [n] = x [n] - \frac{1}{3} w [n - 1] - \frac{1}{5} w [n - 3]$ $y [n] = w [n - 1]$

Step 3: Draw the Direct Form II realization We lay out three delays in series down the center. Because $a_{2} = 0$ , we omit the feedback multiplier tap at the second delay stage. Because $b_{0}, b_{2}, b_{3} = 0$ , we do not tap those nodes for the output sum; the output $y [n]$ is taken directly from the output of the first delay node $w [n - 1]$ !

               Input x[n]
                   |
                   v
               +-------+
               |   +   | <-------------------------+
               +-------+                           |
                   |                               |
                   v w[n]                          |
               +-------+                           |
               |  z^-1 |                           |
               +-------+                           |
                   |---- w[n-1] ------------------>+-----> Output y[n]
                   |             \ (b1 = 1)        |
                   v              v                | ( -a3 = -1/5 )
             ( -a1 = -1/3 )      ( + )             |
       +<----( -1/3 )              ^               |
       |                           |               |
       |           |               | (b2 = 0)      |
       |           v               |               |
       |       +-------+           |               |
       |       |  z^-1 |           |               |
       |       +-------+           |               |
       |           |               |               |
       |           v w[n-2] -------+               |
       |           |                               |
       |           v                               |
       |       +-------+                           |
       |       |  z^-1 |                           |
       |       +-------+                           |
       |           |---- w[n-3]                    |
       |           |                               |
       +<----------+------( -1/5 )---------------->+

5. System Interconnections

LTI systems are connected in multi-block structures. We analyze their combined behavior using mathematical operators:

graph LR
    subgraph Cascade Connection
    c_in[x] --> c_h1[h1] --> c_mid[w] --> c_h2[h2] --> c_out[y]
    end
    
    subgraph Parallel Connection
    p_in[x] --> p_h1[h1] --> p_add((+))
    p_in --> p_h2[h2] --> p_add --> p_out[y]
    end

5.1 Cascade (Series) Connection

Time-Domain Impulse Response: The overall impulse response is the convolution of individual impulse responses: $h_{total} (t) = h_{1} (t) * h_{2} (t)$
Laplace/Z-Domain Transfer Function: Corresponds to algebraic multiplication of their individual transfer functions: $H_{total} (s) = H_{1} (s) \cdot H_{2} (s) ⟺ H_{total} (z) = H_{1} (z) \cdot H_{2} (z)$
Commutative Benefit: Because convolution is commutative, the order of blocks in a cascade does not affect the overall LTI system response.

5.2 Parallel Connection

Time-Domain Impulse Response: The overall impulse response is the algebraic sum of individual impulse responses: $h_{total} (t) = h_{1} (t) + h_{2} (t)$
Laplace/Z-Domain Transfer Function: Corresponds to the sum of their transfer functions: $H_{total} (s) = H_{1} (s) + H_{2} (s) ⟺ H_{total} (z) = H_{1} (z) + H_{2} (z)$

6. Obsidian Desmos Visualization: Integrator & Delay Magnitude Response

To understand how cascading blocks impacts system gain (like low-pass filtering), view the frequency magnitude responses:

height=300; width=100%;
---
y = 1 / sqrt(1 + x^2) | GREEN | label: Single Stage RC
y = 1 / (1 + x^2) | BLUE | label: Cascaded 2-Stage RC

7. End-of-Note Master Review

⚠️ Common Mistakes That Cost Marks

The Feedback Sign Flip Trap: When moving from a difference equation to a block diagram, feedback coefficients are negated. For example, if the equation has $+ 3 y [n - 1]$ , the multiplier block gain must be $- 3$ . If the equation has $- 2 y [n - 1]$ , the multiplier block gain is $+ 2$ .
The Integrator-Delay Swap: Drawing continuous-time blocks (integrators $[1/ s]$ ) when asked to realize discrete difference equations, or drawing delay registers $[z^{- 1}]$ for continuous differential equations.
Non-Canonic Bloat: Drawing a Direct Form I structure when the exam question explicitly asks for a canonic representation. Direct Form II is canonic; Direct Form I is not.

⚗️ ECE 2108 Lab Connection

In the ECE 2108 Laboratory, block realizations are modeled in MATLAB using state-space variables and the tf (transfer function) object commands:

% MATLAB script to define and test a transfer function block cascade
num1 = [1 -1 -6]; den1 = [1 2 1];
sys1 = tf(num1, den1); % Create system TF
is_stable = isstable(sys1); % Check system stability
bode(sys1); % Plot frequency magnitude and phase spectra

🔍 Verbatim PYQ Bank

KUET ECE 2107:

Draw the block diagram of the system described by: $\frac{d ^{2} y ( t )}{d t ^{2}} + 3 y (t) = \frac{d x ( t )}{d t} + 2 \frac{d ^{2} x ( t )}{d t ^{2}}$ Answer Plan: Divide by highest derivative coefficient ( $a_{0} = 1$ ). Note that $a_{1} = 0$ , $a_{2} = 3$ , $b_{0} = 2$ , $b_{1} = 1$ , $b_{2} = 0$ . Draw Direct Form II center delay with shared integrators.

KUET ECE 2107:

Draw the block diagram for: $\frac{d ^{2} y}{d t ^{2}} + 2 \frac{d y}{d t} + y (t) = \frac{d ^{2} x}{d t ^{2}} - \frac{d x}{d t} - 6 x (t)$ Answer Plan: Refer directly to the fully solved Numerical 1 in Section 4.

🏆 Self-Check Before Moving On

Can you explain the exact difference between canonic (Direct Form II) and non-canonic (Direct Form I) realizations?
Do you remember to divide all coefficients by $a_{0}$ if $a_{0} \neq = 1$ ?
Can you trace the feedback paths and apply the correct sign negations?

References: (K. Deergha Rao) Signals and Systems, Ch 2, Pg 93–95; Rabiul Sir Lecture Notes, Lec 7, Pg 27–28; KUET ECE 2107 Past Papers (2025, 2024, 2022).

007_index

2.05 Block Diagram Representations and System Interconnectio

2.05 Block-Diagram Representations & System Interconnections

1. Basic Building Blocks of LTI Systems

1.1 Continuous-Time (CT) Realization Blocks

1.2 Discrete-Time (DT) Realization Blocks

2. Realization of Continuous-Time Systems (LCCDEs)

2.1 Direct Form I Realization (Non-Canonic)

2.2 Direct Form II Realization (Canonic)

3. Realization of Discrete-Time Systems (Difference Equations)

3.1 Discrete Direct Form I

3.2 Discrete Direct Form II (Canonic)

4. Step-by-Step Solved Numericals

📝 Numerical 1: Continuous-Time Realization (KUET 2024, 2022)

Step-by-Step Solution:

📝 Numerical 2: Discrete-Time Realization with “Trap” Coefficients (KUET 2025, 2019)

Step-by-Step Solution:

5. System Interconnections

5.1 Cascade (Series) Connection

5.2 Parallel Connection

6. Obsidian Desmos Visualization: Integrator & Delay Magnitude Response

7. End-of-Note Master Review

⚠️ Common Mistakes That Cost Marks

⚗️ ECE 2108 Lab Connection

🔍 Verbatim PYQ Bank

🏆 Self-Check Before Moving On

Graph View

Table of Contents

Backlinks