missed_portions

ECE 2103 Digital Electronics - Missed Portions & Pedagogical Gaps

This document logs all fundamental concepts, methodologies, and circuits that were missing or insufficiently explained in the original study notes. Adding these sections will make the notes 100% self-sufficient for a student studying Digital Electronics for the first time, while keeping them strictly aligned with the ECE 2103 Syllabus and Checklist.

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1. Chapter 1: Number Systems & Arithmetic

1.1 Unsigned Binary Multiplication Methodology

• Concept: Binary multiplication is mathematically identical to decimal multiplication but utilizes base-2. The process involves generating partial products for each bit of the multiplier and summing them.
• Step-by-Step Algorithm (Paper-and-Pencil):
  1. Write down the multiplicand and multiplier.
  2. For each digit of the multiplier (starting from LSB to MSB):
     • If the multiplier bit is 1, copy the multiplicand (shifted left by the corresponding position weight).
     • If the multiplier bit is 0, write a row of 0s.
  3. Sum all the partial product rows using binary addition rules.

Worked Example: Multiply $11_{10}$ by $5_{10}$ in Binary ($1011_2\times 0101_2$)

       1011   (Multiplicand = 11)
     x 0101   (Multiplier = 5)
     ------
       1011   (Partial Product 1: Multiplier LSB = 1)
      0000.   (Partial Product 2: Multiplier bit = 0, shifted left)
     1011..   (Partial Product 3: Multiplier bit = 1, shifted left 2)
    0000...   (Partial Product 4: Multiplier MSB = 0, shifted left 3)
    -------
    0110111   (Add all rows: 110111_2 = 32 + 16 + 4 + 2 + 1 = 55_10)

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1.2 Unsigned Binary Division Methodology

• Concept: Binary division is performed using long division, which is much simpler than decimal division because the quotient bits can only be 0 or 1.
• Step-by-Step Algorithm (Paper-and-Pencil):
  1. Align the divisor with the MSB of the dividend.
  2. Compare the divisor with the selected portion of the dividend:
     • If the dividend portion is $\ge$ divisor, write 1 in the quotient, subtract the divisor, and bring down the next bit.
     • If the dividend portion is $<$ divisor, write 0 in the quotient and bring down the next bit.
  3. Repeat until all bits of the dividend have been processed.

Worked Example: Divide $45_{10}$ by $9_{10}$ in Binary ($101101_2÷1001_2$)

           000101   (Quotient = 5_10)
        _________
  1001 | 101101   (Dividend = 45_10)
       - 1001     (1011 >= 1001 -> Quotient bit = 1, subtract)
       ------
         00100    (Remainder + bring down next bit '0')
       - 00000    (100 < 1001 -> Quotient bit = 0, subtract 0)
       -------
          1001    (Remainder + bring down next bit '1')
        - 1001    (1001 >= 1001 -> Quotient bit = 1, subtract)
        ------
          0000    (Remainder = 0, Stop)

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2. Chapter 2: Digital Codes & Error Detection

2.1 Alphanumeric Codes: ASCII Overview

• Concept: Digital systems must process non-numeric data such as letters, punctuation, and control characters. ASCII (American Standard Code for Information Interchange) is the universal alphanumeric standard.
• Key Parameters:
  • Standard ASCII: A 7-bit code representing $2^7=128$ unique characters (codes $0\to 127_{10}$). Contains 94 printable characters and 34 non-printable control characters (like Backspace, Carriage Return).
  • Extended ASCII: An 8-bit code representing $2^8=256$ characters, adding graphical symbols and foreign characters.
  • Parity Integration: Standard ASCII is typically stored in 8-bit bytes where the 8th (MSB) bit is reserved as a parity bit for error detection.

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3. Chapter 3: Boolean Algebra & Logic Simplification

3.1 5-Variable K-Map Minimization Methodology

• Concept: A 5-variable function $F(A,B,C,D,E)$ requires $2^5=32$ minterms. Instead of a complex 3D grid, we use two standard 4-variable K-maps:
  • Map 1: Labeled for $A=0$ (contains minterms $0\to 15$).
  • Map 2: Labeled for $A=1$ (contains minterms $16\to 31$).

5-Variable K-Map Layout (Planes A = 0 and A = 1):
        A = 0 (m0 - m15)                     A = 1 (m16 - m31)
            BC                                   BC
        00  01  11  10                       00  01  11  10
      +---+---+---+---+                    +---+---+---+---+
   00 | 0 | 1 | 3 | 2 |                 00 |16 |17 |19 |18 |
      +---+---+---+---+                    +---+---+---+---+
   01 | 4 | 5 | 7 | 6 |                 01 |20 |21 |23 |22 |
DE    +---+---+---+---+                 DE +---+---+---+---+
   11 |12 |13 |15 |14 |                 11 |28 |29 |31 |30 |
      +---+---+---+---+                    +---+---+---+---+
   10 | 8 | 9 |11 |10 |                 10 |24 |25 |27 |26 |
      +---+---+---+---+                    +---+---+---+---+

• Adjacency Rule (Plane Overlay):
  • Cells in the same row and column position across the two maps are physically adjacent (differ by only one variable, $A$).
  • A group can span both planes. If a group of cells exists in the exact same positions on both the $A=0$ and $A=1$ maps, the variable $A$ changes state and is eliminated.
  • If a group exists only on the $A=0$ plane, the final term must include $A^{\prime }$. If it exists only on the $A=1$ plane, it must include $A$.

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4. Chapter 4: Universal Gates & Advanced Logic Families

4.1 Diode Logic Gates (Diode OR & Diode AND)

Before transistors, logic gates were built using PN-junction diodes.

1. Diode OR Gate

• Schematic: Diodes connected from inputs to output node; resistor $R$ pulls output to Ground.
• Circuit Operation:
  • Inputs A, B = LOW (0V): Both diodes reverse-biased (OFF). No current flows. Output pulled to Ground ($0\text{V}⟹\text{Logic }0$).
  • Input A = HIGH (5V), B = LOW: Diode $D_A$ forward-biased (ON), conducting current to output. Diode $D_B$ is OFF. Output rises to $5\text{V}-V_D\approx 4.3\text{V}⟹\text{Logic }1$.

Diode OR Gate Schematic:
  Input A --->[ Diode DA ]---+---> Output Y
                             |
  Input B --->[ Diode DB ]---+
                             |
                             [ R ]
                             |
                            GND

2. Diode AND Gate

• Schematic: Diodes pointing from output node back to inputs; resistor $R$ pulls output to $V_{CC}$ (5V).
• Circuit Operation:
  • ANY Input (A or B) = LOW (0V): The corresponding diode is forward-biased, conducting current to Ground. This pulls the output node down to $0\text{V}+V_D\approx 0.7\text{V}⟹\text{Logic }0$.
  • BOTH Inputs (A and B) = HIGH (5V): Both diodes are reverse-biased (OFF). No current flows through them. Output node is pulled up to $V_{CC}=5\text{V}⟹\text{Logic }1$.

Diode AND Gate Schematic:
                             Vcc (5V)
                                |
                                [ R ]
                                |
  Input A <---[ Diode DA ]------+---> Output Y
                                |
  Input B <---[ Diode DB ]------+

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4.2 CMOS NOR Gate

• Concept: CMOS NOR logic uses PMOS transistors in series (Pull-Up Network) and NMOS transistors in parallel (Pull-Down Network).
• Circuit Operation:
  • ANY Input (A or B) = HIGH (5V): The parallel NMOS stack ($N_A$ or $N_B$) turns ON, pulling the output node to Ground (Logic 0). At least one series PMOS ($P_A$ or $P_B$) turns OFF, disconnecting the path to $V_{DD}$.
  • BOTH Inputs (A and B) = LOW (0V): Both parallel NMOS turn OFF. Both series PMOS turn ON, creating a low-resistance path from $V_{DD}$ to Output (Logic 1).

CMOS NOR Schematic:
                     Vdd (5V)
                        |
                     [ PMOS PA ]
                        |
                     [ PMOS PB ]
                        |
      Inputs A, B ----+--+----------> Output Y
                      |  |
                  +---+--+---+
                  |          |
             [ NMOS NA ] [ NMOS NB ]
                  |          |
                  +----+-----+
                       |
                      GND

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4.3 ECL (Emitter-Coupled Logic) OR/NOR Gate

• Concept: ECL is a high-speed, non-saturating bipolar logic family. It avoids saturation delays by using a differential amplifier configuration.
• Circuit Operation:
  • The inputs drive the base terminals of parallel input transistors ($T_A,T_B$).
  • Their emitters are tied together and connected to a constant-current source (resistor to $-V_{EE}$).
  • A reference transistor ($T_{REF}$) has its base connected to a fixed reference voltage ($V_{BB}$).
  • Logic LOW Input: If inputs are low, $T_A,T_B$ are OFF. Current is steered entirely through $T_{REF}$. Emitter follower outputs generate $Y=\text{LOW}$ and $Y^{\prime }=\text{HIGH}$.
  • Logic HIGH Input: If any input is high, $T_A$ or $T_B$ turns ON, steering current away from $T_{REF}$. The emitter follower outputs flip: $Y=\text{HIGH}$ (OR output) and $Y^{\prime }=\text{LOW}$ (NOR output).

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5. Chapter 5: Combinational Circuit Design

5.1 Combinational Circuit Analysis Blueprint

• Concept: Analysis is the reverse-engineering process of determining the logical function of a given schematic.
• The 4-Step Analysis Algorithm:
  1. Label Outputs: Assign variable labels to all intermediate gate outputs.
  2. Write Equations: Deriving from the input side forward, write the Boolean equation for each intermediate output, and finally for the overall circuit outputs.
  3. Construct Truth Table: Calculate the binary output states for all $2^n$ possible input combinations using the derived equations.
  4. Determine Function: Analyze the truth table or simplify the Boolean equation to describe what function the circuit performs (e.g., parity checker, adder, etc.).

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5.2 BCD to Seven-Segment Decoder Design

• Concept: Converts a 4-bit BCD input ($A,B,C,D$) to control signals for a 7-segment display (segments $a,b,c,d,e,f,g$) representing digits 0 to 9.
• Display Layout:

      a
    +---+
  f |   | b
    +---+  <- g
  e |   | c
    +---+
      d

• Truth Table (Active-High Display):
  • Don’t care inputs ($10\to 15$): Segments are blank or don’t care ($X$).

Decimal	Inputs ($ABCD$)	Segments ($abcdefg$)
0	0 0 0 0	1 1 1 1 1 1 0
1	0 0 0 1	0 1 1 0 0 0 0
2	0 0 1 0	1 1 0 1 1 0 1
3	0 0 1 1	1 1 1 1 0 0 1
4	0 1 0 0	0 1 1 0 0 1 1
5	0 1 0 1	1 0 1 1 0 1 1
6	0 1 1 0	1 0 1 1 1 1 1
7	0 1 1 1	1 1 1 0 0 0 0
8	1 0 0 0	1 1 1 1 1 1 1
9	1 0 0 1	1 1 1 1 0 1 1

• Minimized Logic Equations (using K-Maps):
  • $a=A+C+BD+B^{\prime }{D}^{\prime }$
  • $b=B^{\prime }+C^{\prime }{D}^{\prime }+CD$
  • $c=B+C^{\prime }+D$
  • $d=A+B^{\prime }{D}^{\prime }+C{D}^{\prime }+B^{\prime }C+B{C}^{\prime }D$
  • $e=B^{\prime }{D}^{\prime }+C{D}^{\prime }$
  • $f=A+C^{\prime }{D}^{\prime }+B{C}^{\prime }+B{D}^{\prime }$
  • $g=A+B^{\prime }C+B{C}^{\prime }+C{D}^{\prime }$

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5.3 Basic 1-to-4 Demultiplexer (DeMUX) Design

• Concept: A Demultiplexer takes a single input line $D$ and routes it to one of $2^n$ outputs controlled by $n$ select lines.
• 1-to-4 DeMUX Truth Table:
  • Inputs: Data $D$, Selects $S_1,S_0$. Outputs: $Y_3,Y_2,Y_1,Y_0$.

Selects ($S_1{S}_0$)	Outputs ($Y_3{Y}_2{Y}_1{Y}_0$)
0 0	0 0 0 D
0 1	0 0 D 0
1 0	0 D 0 0
1 1	D 0 0 0

• Logic Equations:
  • $Y_0=S_1^{\prime }{S}_0^{\prime }D$
  • $Y_1=S_1^{\prime }{S}_{0}D$
  • $Y_2=S_1{S}_0^{\prime }D$
  • $Y_3=S_1{S}_{0}D$
• Schematic: Four 3-input AND gates driven by select signals and Data input.