04 Chapter 4 - Universal Gates & Advanced Logic Families (Merged)

Chapter 4: Universal Gates & Advanced Logic Families - Complete Study Notes

NotebookLM Ingestion Compilation

This merged document contains all 7 study notes for Chapter 4: Universal Gates & Advanced Logic Families from ECE 2103 Digital Electronics (Sharif Sir).

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Related Concepts: 02 Universal Logic Gates & 2-Level Implementations | 03 BJT as NOT Gate & Inverter Operation | 06 CMOS Logic & Logic Gate Characteristics

4.01 Digital Systems & Signal Propagation

What is a Digital System?

A Digital System is an electronic system that processes, stores, and transmits information represented in discrete binary states {typically logic 0 (0V) and logic 1 (5V or 3.3V)}, as opposed to Analog Systems which process continuous physical quantities.

graph TD
    subgraph Digital Advantages
        D[Digital System Benefits] --> A1[1. Superior Noise Immunity]
        D --> A2[2. Ease of Programmability]
        D --> A3[3. High Scalability & IC Integration]
        D --> A4[4. Exact Reproduction & Storage]
    end

    subgraph Signal Transmission Channel Model
        Tx[Transmitter: Ideal Digital Pulse] --> Channel[Transmission Channel / PCB Trace]
        Channel -->|Attenuation & Parasitic Capacitance| Degradation[Degraded Signal: Lowers Amplitude & Rounds Edges]
        Degradation --> Rx[Receiver Gate: Needs Noise Margin]
    end

---

1. Nine Engineering Advantages of Digital Systems

1. Superior Noise Immunity: Discrete threshold levels make digital signals far less susceptible to external noise corruption than continuous analog signals.
2. Ease of Programmability: System operations are dictated by software and firmware code rather than fixed hardware modifications.
3. High Integration Density (VLSI): Millions of transistors can be fabricated onto a single silicon die.
4. Exact Signal Reproduction & Storage: Binary data can be stored permanently in RAM/Flash without quality degradation.
5. Enhanced Security & Cryptography: Binary streams are easily encrypted using digital ciphers {e.g., XOR masks}.
6. Cost-Effective Mass Production: Standardized CMOS fabrication reduces per-gate costs.
7. Simplified System Design: Modular logic gate building blocks eliminate complex analog bias calculations.
8. High Reliability & Precision: Output precision is increased simply by increasing bit-width.
9. Direct Compatibility with Microprocessors: Native binary alignment with CPUs and digital signal processors (DSPs).

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2. Signal Propagation & Physical Distortion

When a digital pulse travels across a transmission line or PCB copper trace, it experiences physical degradation due to channel parasitics:

• Attenuation: The gradual reduction in voltage amplitude caused by trace resistance.
• Phase Shift / Dispersion: Propagation delay differences across frequency components, causing pulse rounding and inter-symbol interference (ISI).

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3. Propagation Delay & System Performance

In physical digital circuits, electrical signals do not travel instantaneously. Every logic gate introduces a tiny delay between when an input changes and when the output stabilizes.

3.1 Propagation Delay ($t_{pd}$)

• Definition: The time interval required for a signal transition on an input terminal to propagate through a logic gate and produce a corresponding transition on its output terminal. Usually measured in nanoseconds (ns).
• Rise/Fall Delay: Gates often have different delays depending on whether the output is rising ($t_{pLH}$) or falling ($t_{pHL}$). The average propagation delay is: $t_{pd}=\frac{t_{pLH}+t_{pHL}}{2}$

3.2 The Cascading Accumulation Rule (Critical Path)

When gates are connected in series, their individual propagation delays add up directly.

Propagation Delay Accumulation:
 Vin ---> [ Gate 1 ] ---> [ Gate 2 ] ---> [ Gate 3 ] ---> Vout
            t_pd1          t_pd2          t_pd3

In a synchronous digital system, the overall speed is limited by the longest path (the Critical Path) from any input to any output:

$t_{total}=t_{pd1}+t_{pd2}+\cdots +t_{pdN}$

3.3 Maximum Operating Frequency ($f_{max}$)

The maximum clock frequency at which a digital system can operate safely without timing violations is determined by the total propagation delay of the critical path:

$f_{max}=\frac{1}{t_{total}}$

Reducing the number of gate levels in the critical path (logic minimization) is done not just to save chip area and manufacturing costs, but also to directly increase the clock speed of the processor.

3.4 Comparison: Rise Time vs. Fall Time vs. Propagation Delay

Feature	Rise Time ($t_r$)	Fall Time ($t_f$)	Propagation Delay ($t_{pd}$)
Definition	Time required for output voltage to rise from 10% to 90% of its final HIGH level.	Time required for output voltage to fall from 90% to 10% of its initial HIGH level.	Time interval between input transition (at 50%) and corresponding output transition (at 50%).
Points of Measurement	$10\%$ to $90\%$ of output signal amplitude.	$90\%$ to $10\%$ of output signal amplitude.	$50\%$ input amplitude to $50\%$ output amplitude.
Physical Cause	Time taken to charge load/parasitic capacitance through pull-up transistor.	Time taken to discharge load/parasitic capacitance through pull-down transistor.	Time taken for internal transistors to switch states (carrier transport & storage delays).
Symmetry	Often slower than $t_f$ in CMOS because PMOS mobility is lower than NMOS.	Often faster than $t_r$ in CMOS because NMOS mobility is higher.	Average of low-to-high and high-to-low transitions ($t_{pd}=\frac{t_{pLH}+t_{pHL}}{2}$).
System Impact	Limits the sharpness/slope of rising clock edges.	Limits the sharpness/slope of falling clock edges.	Limits the maximum clock frequency of the system ($f_{max}=1/t_{total}$).

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4. Past Year Questions (PYQs) [PYQ 2020, 2024, 2025]

• [PYQ 2020, 2024, 2025]: Advantages of digital systems over analog systems. (07 to 10 Marks)
• [Class Test Q&A]: Describe signal propagation phenomena and transmission line degradation.

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Related Concepts: 01 Digital Systems & Signal Propagation | 03 BJT as NOT Gate & Inverter Operation | 05 TTL Logic Families & Open Collector Bus Systems

4.02 Universal Logic Gates & 2-Level Implementations

What is a Universal Logic Gate?

A logic gate is classified as Universal if any arbitrary Boolean function or digital circuit can be constructed using only that single gate type, without requiring any other gate types.

Both NAND and NOR gates are Universal Gates.

graph TD
    subgraph 4-NAND Gate XOR Network
        InA[Input A] & InB[Input B] --> NAND1[NAND 1: Output N1 = AB']
        InA & NAND1 --> NAND2[NAND 2: Output N2 = A • N1 ']
        InB & NAND1 --> NAND3[NAND 3: Output N3 = B • N1 ']
        NAND2 & NAND3 --> NAND4[NAND 4: Output F = A ⊕ B]
    end

---

1. NAND & NOR Gate Realizations of Basic Gates

Target Gate	NAND Gates Required	NOR Gates Required
NOT	1 (inputs tied: $\overline{A\cdot A}=A^{\prime }$)	1 (inputs tied: $\overline{A+A}=A^{\prime }$)
AND	2 ($\overline{\overline{AB}}=AB$)	3 ($\overline{A^{\prime }+B^{\prime }}=AB$)
OR	3 ($\overline{A^{\prime }\cdot B^{\prime }}=A+B$)	2 ($\overline{\overline{A+B}}=A+B$)
XOR	4 (cascaded 4-NAND network)	5 (4-NOR XNOR + 1 NOR Inverter)
XNOR	5 (4-NAND XOR + 1 NAND Inverter)	4 (cascaded 4-NOR network)

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2. Two-Level Gate Implementation Rules

A. Two-Level NAND-NAND Implementation (SOP)

• Rule: Any function in Sum of Products (SOP) form can be directly implemented using a 2-level NAND-NAND circuit.
• Proof: $F=AB+CD⟹F=((AB+CD{)}^{\prime }{)}^{\prime }=((AB{)}^{\prime }\cdot (CD{)}^{\prime }{)}^{\prime }$. This represents a final NAND gate taking inputs from two level-1 NAND gates.
• Direct Literals Rule: If a single literal (e.g., $E$) feeds directly into the second-level OR/NAND gate, it must be complemented ($E^{\prime }$) to cancel out the output gate’s inversion.

B. Two-Level NOR-NOR Implementation (POS)

• Rule: Any function in Product of Sums (POS) form can be directly implemented using a 2-level NOR-NOR circuit.
• Proof: $F=(A+B)(C+D)⟹F=(((A+B)(C+D){)}^{\prime }{)}^{\prime }=((A+B{)}^{\prime }+(C+D{)}^{\prime }{)}^{\prime }$. This represents a final NOR gate taking inputs from two level-1 NOR gates.

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3. Two-Level Implementation Geometry (Degenerate vs. Non-Degenerate)

When cascading gates to build multi-level networks, the logical operations performed at each level determine whether the circuit is useful or redundant.

If we analyze all two-level gate combinations using four basic gates (AND, OR, NAND, NOR), there are $4\times 4=16$ possible configurations:

Level 1 Gate	Level 2: AND	Level 2: OR	Level 2: NAND	Level 2: NOR
AND	Degenerate	AND-OR	AND-NAND	AND-NOR
OR	OR-AND	Degenerate	OR-NAND	OR-NOR
NAND	NAND-AND	NAND-OR	NAND-NAND	Degenerate
NOR	NOR-AND	NOR-OR	Degenerate	NOR-NOR

• Degenerate Forms (8 combinations): These are combinations where the second-level gate performs the exact same logical operation as the first-level gates (e.g., AND-AND, OR-OR, NAND-NOR). They are mathematically redundant because the entire two-level circuit simplifies (degenerates) into a single-level gate with multiple inputs.
• Non-Degenerate Forms (8 combinations): These configurations maintain two distinct levels of logic processing. The most important for hardware synthesis are:
  • NAND-NAND: Equivalent to AND-OR (implements Sum-of-Products).
  • NOR-NOR: Equivalent to OR-AND (implements Product-of-Sums).

3.1 Comparison: Degenerate vs. Non-Degenerate Logic Configurations

Feature	Degenerate Logic Configurations	Non-Degenerate Logic Configurations
Logic Levels	Collapses mathematically into a single level of logic.	Maintains two distinct levels of logic processing.
Algebraic Simplification	$F=(AB)(CD)=ABCD$ (simplifies to a single product/sum).	Cannot be simplified to a single-level operator.
Gate Count Reduction	Reduces to a single multi-input gate.	Requires both level-1 and level-2 gates.
Examples (out of 16)	AND-AND, OR-OR, NAND-NOR, NOR-NAND.	AND-OR, OR-AND, NAND-NAND, NOR-NOR.
Hardware Synthesis Value	Redundant. No practical value for multi-level logic design.	Fundamental. NAND-NAND and NOR-NOR are the standard methods for universal implementations.

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4. Universal Gate Implementation (Bubble-Pushing Algorithm)

Bubble-pushing is a graphical method used to convert a standard AND-OR logic circuit into an all-NAND or all-NOR equivalent circuit without changing the logical function.

4.1 Theoretical Basis: Double Inversion

The mathematical foundation of gate conversion is the double negation rule:

$F=(F^{\prime \prime })=\overline{\overline{F}}$

By applying De Morgan’s theorem, we can convert product terms to sum terms and vice-versa.

4.2 NAND-NAND Conversion (Bubble-Pushing Steps)

To convert a standard two-level AND-OR circuit into a NAND-only circuit:

1. Draw the logic circuit in its standard AND-OR form.
2. Place a bubble (inversion circle) at the output of every first-level AND gate.
3. To compensate for these bubbles, place a bubble at every input of the second-level OR gate.
4. Redraw the bubbled-input OR gate as a NAND gate (since $(\overline{A}+\overline{B})=\overline{A\cdot B}$ by De Morgan’s Law).
5. If any single input goes directly to the second-level gate without passing through a first-level gate, insert a NOT gate (configured as a NAND inverter) on that line to compensate for the added bubble.

AND-OR to NAND-NAND Conversion Flow:
Step 1 (Original):   Inputs ---> [ AND ] ---> Output Gate [ OR ] ---> F
Step 2 (Bubble):     Inputs ---> [ AND ]o ---> o Output Gate [ OR ] ---> F
Step 3 (NAND Gate):  Inputs ---> [ NAND ] ---> [ NAND ] ---> F

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5. Major Exam Proofs

Major PYQ Proof: 5-Gate NOR XOR Circuit (2015, 2021 - 8 Marks)

Question: Show mathematically that a 5-gate NOR network acts as an Exclusive-OR (XOR) gate.

Proof Solution:

1. $N_1=\overline{A+B}$
2. $N_2=\overline{A+N_1}=\overline{A+(A+B{)}^{\prime }}=\overline{A+A^{\prime }{B}^{\prime }}=A^{\prime }\cdot (A+B)=A^{\prime }B$
3. $N_3=\overline{B+N_1}=\overline{B+(A+B{)}^{\prime }}=\overline{B+A^{\prime }{B}^{\prime }}=B^{\prime }\cdot (A+B)=A{B}^{\prime }$
4. $N_4=\overline{N_2+N_3}=\overline{A^{\prime }B+A{B}^{\prime }}=A\odot B\text{(XNOR)}$
5. $N_5=\overline{N_4}=\overline{A\odot B}=\mathbf{A}\oplus \mathbf{B}\text{(XOR)}■$

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PYQ Master Design (2015): The 2-NOR Gate Limit Puzzle

Question: Implement $F=A^{\prime }{B}^{\prime }{C}^{\prime }+A{B}^{\prime }D+A^{\prime }{B}^{\prime }C{D}^{\prime }$, with don’t cares $d=ABC+A{B}^{\prime }{D}^{\prime }$, using no more than Two NOR gates. Assume normal and complement inputs are available.

Step 1: Expand into Minterms We translate the raw algebra into decimal minterms to safely plot a K-map:

• $A^{\prime }{B}^{\prime }{C}^{\prime }\to 000X\to 0,1$
• $A{B}^{\prime }D\to 10X1\to 9,11$
• $A^{\prime }{B}^{\prime }C{D}^{\prime }\to 0010\to 2$
• Minterms = $\Sigma m(0,1,2,9,11)$
• $ABC\to 111X\to 14,15$
• $A{B}^{\prime }{D}^{\prime }\to 10X0\to 8,10$
• Don’t Cares = $\Sigma d(8,10,14,15)$

Step 2: Group the Zeros ($F^{\prime }$) for NOR Logic Because a NOR gate generates inverted OR logic $(X+Y{)}^{\prime }$, we simplify for $F^{\prime }$ (the zeros on the K-map). The zeros are remaining cells: $3,4,5,6,7,12,13$.

• Grouping $(4,5,6,7)$ with $(12,13,14d,15d)$ creates an 8-cell block: $B$
• Grouping $(3)$ with $(7)$ creates a pair: $A^{\prime }CD$
• Simplified complement: $F^{\prime }=B+A^{\prime }CD$

Step 3: The 2-NOR Implementation Double complementing gives $F$: $F=(B+A^{\prime }CD{)}^{\prime }$

• NOR Gate 1: Feed $A,C^{\prime },$ and $D^{\prime }$ into the first NOR gate: ${\text{Output}}_1=(A+C^{\prime }+D^{\prime }{)}^{\prime }={\mathbf{A}}^{\prime }\mathbf{CD}$
• NOR Gate 2: Feed $B$ and ${\text{Output}}_1$ into the second NOR gate: ${\text{Output}}_2=(B+{\text{Output}}_1{)}^{\prime }=(\mathbf{B}+{\mathbf{A}}^{\prime }\mathbf{CD}{)}^{\prime }=\mathbf{F}$

Proof Complete: Implemented using exactly two NOR gates! $■$

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Past Year Questions (PYQs)

• [PYQ 2021]: Prove NOR is a universal gate with basic gate implementations. (08 Marks)
• [PYQ 2015, 2021]: 5-gate NOR XOR circuit proof. (08 Marks)
• [PYQ 2015, 2021]: Implement $F=A^{\prime }{B}^{\prime }{C}^{\prime }+A{B}^{\prime }D+A^{\prime }{B}^{\prime }C{D}^{\prime }$ with no more than two NOR gates. (12 Marks)

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Related Concepts: 01 Digital Systems & Signal Propagation | 04 NPN Transistor Basics & DTL Logic | 05 TTL Logic Families & Open Collector Bus Systems

4.03 BJT as NOT Gate & Inverter Operation

BJT Transistor Switch Concept

In digital logic, a Bipolar Junction Transistor (BJT) operates strictly as a digital switch driven between two extreme operating states:

1. Cut-off Region (OFF Switch): Base-Emitter junction reverse-biased $⟹I_B=0,I_C=0,V_{out}=V_{CC}$ (Logic HIGH).
2. Saturation Region (ON Switch): Base-Emitter junction forward-biased $⟹I_B\ge I_{B(sat)},V_{out}=V_{CE(sat)}\approx 0.2\text{V}$ (Logic LOW).

BJT Inverter Circuit Schematic:
                     Vcc (5V)
                        |
                        [ Rc ]
                        |
 Vin ---> [ Rb ] --->|/  Collector (Vout)
                     |\
                        v Emitter
                        |
                       GND

graph TD
    Input[Input Voltage Vin] --> Check{Vin Level}
    
    Check -->|Vin = LOW e.g. 0.2V| Cutoff[Cut-off Region: BE Junction OFF]
    Cutoff --> ICZero[Collector Current IC = 0]
    ICZero --> OutHigh[Output Vout = VCC = HIGH Logic 1]
    
    Check -->|Vin = HIGH e.g. 5V| Saturation[Saturation Region: BE Junction ON]
    Saturation --> ICSat[Max Collector Current IC-sat]
    ICSat --> OutLow[Output Vout = VCE-sat = 0.2V = LOW Logic 0]

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1. Mathematical Saturation & Cut-off Proof

Major Exam Numerical Problem (2016, 2019 - 13 Marks)

Given Circuit Parameters:

• $V_{CC}=5\text{V}$, $V_{in(HIGH)}=5\text{V}$, $V_{in(LOW)}=0.2\text{V}$
• Base Resistor $R_B=10\text{k}\Omega$, Collector Resistor $R_C=1\text{k}\Omega$
• Minimum Current Gain $h_{FE}(\beta )=30$
• Transistor Constants: $V_{BE(sat)}=0.7\text{V}$, $V_{CE(sat)}=0.2\text{V}$

Part A: Operation when $V_{in}=0.2\text{V}$ (Logic LOW)

1. Base-Emitter voltage $V_{BE}=0.2\text{V}<0.7\text{V}$ {below cut-in threshold}.
2. Transistor is in Cut-off. Base current $I_B=0$, Collector current $I_C=0$.
3. Output voltage: $V_{out}=V_{CC}-(I_C\cdot R_C)=5\text{V}-(0\cdot 1\text{k}\Omega )=5\text{V}(\text{Logic HIGH})$

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Part B: Operation when $V_{in}=5\text{V}$ (Logic HIGH)

1. Calculate actual base current ($I_B$): $I_B=\frac{V_{in}-V_{BE(sat)}}{R_B}=\frac{5\text{V}-0.7\text{V}}{10\text{k}\Omega }=\frac{4.3\text{V}}{10\text{k}\Omega }=0.43\text{ mA}$

2. Calculate saturation collector current ($I_{C(sat)}$): $I_{C(sat)}=\frac{V_{CC}-V_{CE(sat)}}{R_C}=\frac{5\text{V}-0.2\text{V}}{1\text{k}\Omega }=\frac{4.8\text{V}}{1\text{k}\Omega }=4.8\text{ mA}$

3. Calculate minimum base current required for saturation ($I_{B(min)}$): $I_{B(min)}=\frac{I_{C(sat)}}{h_{FE}}=\frac{4.8\text{ mA}}{30}=0.16\text{ mA}$

4. Saturation Condition Check: $I_B(0.43\text{ mA})\ge I_{B(min)}(0.16\text{ mA})$ Since $I_B>I_{B(min)}$, the transistor is driven deep into saturation.

5. Output voltage drops to saturation voltage: $V_{out}=V_{CE(sat)}=0.2\text{V}(\text{Logic LOW})■$

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Past Year Questions (PYQs)

• [PYQ 2016, 2019]: BJT inverter operation: Mathematical proof of saturation/cut-off given circuit parameters. (13 Marks)

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Related Concepts: 03 BJT as NOT Gate & Inverter Operation | 05 TTL Logic Families & Open Collector Bus Systems | 06 CMOS Logic & Logic Gate Characteristics

4.04 Diode Logic & DTL Logic Families

Physical Hardware of Logic

Before analyzing complex integrated logic families like TTL, we study the simplest electronic gate models using semiconductor diodes (Diode Logic), and how they are paired with BJTs to create Diode-Transistor Logic (DTL).

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1. Diode Logic Gates (Diode OR & Diode AND) [Syllabus Week 7]

Foundational Concept (Outside Direct PYQ Scope)

Diode Logic (DL) gates are passive components that represent a foundational step in electronic logic evolution, but they are not directly tested as design problems in ECE 2103 examinations. They serve as required background for Diode-Transistor Logic (DTL).

Diode Logic (DL) is the most basic form of electronic logic gates, using PN-junction diodes as voltage-controlled switches.

A. The Diode OR Gate

Circuit Schematic:

Diodes are connected in parallel from each input node to the output node, with a pull-down resistor $R$ connected to Ground.

Diode OR Gate Schematic:
  Input A --->[ Diode DA (Anode -> Cathode) ]---+---> Output Y
                                                 |
  Input B --->[ Diode DB (Anode -> Cathode) ]---+
                                                 |
                                                 [ R ]
                                                 |
                                                GND

Operation:

• Case 1: Both Inputs A, B = LOW (0V): Diodes $D_A$ and $D_B$ are reverse-biased (OFF). No current flows. The output is pulled down to Ground through resistor $R$ ($Y\approx 0\text{V}⟹\text{Logic }0$).
• Case 2: Input A = HIGH (5V), B = LOW: Diode $D_A$ is forward-biased (ON) and conducts. Diode $D_B$ remains OFF. Current flows through $D_A$ and resistor $R$ to Ground. The output rises to input voltage minus one diode drop ($Y=V_{in}-V_D\approx 5\text{V}-0.7\text{V}=4.3\text{V}⟹\text{Logic }1$).

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B. The Diode AND Gate

Circuit Schematic:

Diodes are connected in parallel pointing from the output node back to the inputs, with a pull-up resistor $R$ connected to $V_{CC}$ (5V).

Diode AND Gate Schematic:
                             Vcc (5V)
                                |
                                [ R ]
                                |
  Input A <---[ Diode DA (Cathode <- Anode) ]------+---> Output Y
                                |
  Input B <---[ Diode DB (Cathode <- Anode) ]------+

Operation:

• Case 1: ANY Input (A or B) = LOW (0V): The corresponding diode is forward-biased (ON) and conducts current to Ground. This clamps the output node to Ground plus one diode drop ($Y=V_{in}+V_D\approx 0\text{V}+0.7\text{V}=0.7\text{V}⟹\text{Logic }0$).
• Case 2: BOTH Inputs A, B = HIGH (5V): Both diodes $D_A$ and $D_B$ are reverse-biased (OFF) because their cathodes are at $5\text{V}$. No current flows through the diodes. The output node is pulled up to $V_{CC}$ through resistor $R$ ($Y=V_{CC}=5\text{V}⟹\text{Logic }1$).

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2. NPN Silicon Transistor Characteristic Curves

A. Base Input Characteristics ($I_B$ vs. $V_{BE}$)

• Curve Behavior: Operates like a forward-biased PN junction diode.
• Key Voltage: Negligible base current flows until $V_{BE}$ reaches cut-in voltage ($\approx 0.6\text{V}$). In saturation, $V_{BE(sat)}\approx 0.7\text{V}-0.8\text{V}$.

B. Collector Output Characteristics ($I_C$ vs. $V_{CE}$)

Divided into three distinct regions:

1. Cut-off Region: $I_B=0⟹I_C\approx 0,V_{CE}\approx V_{CC}$ (OFF Switch).
2. Active Region: Linear amplification region (not used in digital logic).
3. Saturation Region: $V_{CE}$ drops to $V_{CE(sat)}\approx 0.2\text{V}$, $I_C$ reaches maximum limit $I_{C(sat)}$ (ON Switch).

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3. DTL NAND Gate Saturation Proof

Major PYQ Proof: DTL Gate Saturation ( $h_{FE}=20$) (2021, 2022 - 10 Marks)

Given DTL NAND Parameters:

• $V_{CC}=5\text{V}$, $R_1=5\text{k}\Omega$, $R_2=5\text{k}\Omega$, $R_C=2\text{k}\Omega$, $h_{FE}=20$
• Diode drop $V_D=0.7\text{V}$, $V_{BE(sat)}=0.8\text{V}$, $V_{CE(sat)}=0.2\text{V}$

Proof Steps:

1. Input State: All inputs ($A,B,C$) are HIGH ($5\text{V}$) $⟹$ Input diodes are reverse-biased (OFF).

2. Node Voltage $V_P$ (Anode of level-shift diode $D_1$): $V_P=V_{D1}+V_{D2}+V_{BE(sat)}=0.7\text{V}+0.7\text{V}+0.8\text{V}=2.2\text{V}$

3. Current Calculations:

   • Current from $V_{CC}$ through $R_1$: $I_1=\frac{V_{CC}-V_P}{R_1}=\frac{5\text{V}-2.2\text{V}}{5\text{k}\Omega }=0.56\text{ mA}$
   • Current lost to ground through $R_2$: $I_2=\frac{V_{BE(sat)}}{R_2}=\frac{0.8\text{V}}{5\text{k}\Omega }=0.16\text{ mA}$
   • Base current entering transistor ($I_B$): $I_B=I_1-I_2=0.56\text{ mA}-0.16\text{ mA}=0.40\text{ mA}$

4. Saturation Check:

   • Maximum saturation collector current ($I_{C(sat)}$): $I_{C(sat)}=\frac{V_{CC}-V_{CE(sat)}}{R_C}=\frac{5\text{V}-0.2\text{V}}{2\text{k}\Omega }=2.4\text{ mA}$
   • Available collector current drive: $h_{FE}\times I_B=20\times 0.40\text{ mA}=8.0\text{ mA}$

5. Since $8.0\text{ mA}\gg 2.4\text{ mA}$ ($h_{FE}{I}_B\ge I_{C(sat)}$), the output transistor is driven deep into saturation. $■$

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4. Comparison Table: Diode Logic (DL) vs. Diode-Transistor Logic (DTL)

Feature	Diode Logic (DL)	Diode-Transistor Logic (DTL)
Logic Components	Diodes and resistors only.	Diodes, resistors, and Bipolar Junction Transistors (BJTs).
Signal Amplification	None (passive circuitry).	Active (transistor provides current amplification).
Signal Degradation	High. Output voltage drops by $V_D\approx 0.7\text{V}$ per stage (restricts cascading).	Near-zero. Transistor switches completely between $V_{CC}$ and $V_{CE(sat)}\approx 0.2\text{V}$, restoring signal levels.
Fan-out Capability	Very low (loading directly affects output voltage).	High (transistor amplifies current to drive multiple loads).
Logic Operations	AND, OR (cannot implement NOT/inversion).	NAND, NOR, NOT (BJT acts as an inverter).

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5. Past Year Questions (PYQs)

• [PYQ 2022]: Draw and explain Transistor Base and Collector characteristics. (09 Marks)
• [PYQ 2021, 2022]: DTL gate output transistor saturation proof ($h_{FE}=20$). (10 Marks)

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Related Concepts: 03 BJT as NOT Gate & Inverter Operation | 04 NPN Transistor Basics & DTL Logic | 06 CMOS Logic & Logic Gate Characteristics

4.05 TTL Logic Families & Open Collector Bus Systems

Concept Overview: TTL Logic

Transistor-Transistor Logic (TTL) replaced DTL by utilizing multi-emitter transistors at the input stage, achieving much higher switching speeds.

Standard TTL uses a Totem-Pole output for active pull-up and pull-down. Open-Collector TTL removes the active pull-up to allow outputs to be safely tied together for common bus systems.

graph TD
    subgraph TTL NAND Totem-Pole Stages
        InputStage[Input Stage: Multi-Emitter Transistor T1] --> PhaseSplitter[Phase Splitter: Transistor T2]
        PhaseSplitter -->|Inverted Collector Output| PullUp[Active Pull-Up: Transistor T4 + Diode D]
        PhaseSplitter -->|Direct Emitter Output| PullDown[Active Pull-Down: Transistor T3]
        PullUp & PullDown --> OutputNode[Output Y]
    end

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1. Standard TTL NAND Gate Working Principle

• Inputs: Multi-emitter transistor $T_1$.

• Case 1: ANY Input is LOW (0V)

  • Emitter-base junction of $T_1$ is forward-biased $⟹$ current flows out of input pin.
  • Base-collector junction of $T_1$ is reverse-biased $⟹T_2$ turns OFF.
  • $T_2$ OFF $⟹$ pull-down transistor $T_3$ turns OFF.
  • Collector of $T_2$ rises toward $V_{CC}$, driving base of $T_4⟹$ pull-up transistor $T_4$ turns ON.
  • Result: Output pulled HIGH to $V_{CC}$ ($Y=1$).

• Case 2: ALL Inputs are HIGH (5V)

  • Emitter-base junctions of $T_1$ are reverse-biased.
  • Base-collector junction of $T_1$ becomes forward-biased, steering base current into $T_2⟹T_2$ turns ON.
  • $T_2$ ON $⟹$ emitter current drives $T_3$ ON into deep saturation.
  • Collector of $T_2$ drops low $⟹$ pull-up transistor $T_4$ turns OFF (diode $D$ ensures $T_4$ stays OFF).
  • Result: Output pulled LOW to Ground through $T_3$ ($Y=0$).

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2. Totem-Pole Destructive Conflict & Open Collector Gates

Standard TTL gates utilize a “Totem-Pole” output stage consisting of an active pull-up transistor $T_4$ and an active pull-down transistor $T_3$.

2.1 The Destructive Conflict of Totem-Pole Outputs

Connecting the outputs of two standard totem-pole TTL gates directly together is physically forbidden in digital design:

• If Gate A outputs a Logic HIGH (transistor $T_4$ is ON, acting as a virtual short to $V_{CC}$), and Gate B outputs a Logic LOW (transistor $T_3$ is ON, acting as a virtual short to Ground).
• Connecting their output pins directly together creates an extremely low-impedance path directly from $V_{CC}$ of Gate A to Ground of Gate B through the ON transistors:

  Vcc (5V) ---> [ T4 (Gate A) ON ] ---> (Tied Output Node) ---> [ T3 (Gate B) ON ] ---> Ground

• This results in a massive current spike (exceeding maximum power ratings) which instantly overheats and destroys both IC chips.

2.2 The Open Collector TTL Solution

To safely connect multiple outputs to a common wire (e.g., in shared computer bus systems), we use Open Collector gates.

• The active pull-up transistor ($T_4$) and diode ($D$) are completely removed from the output stage.
• The collector of $T_3$ is left unconnected (“open”) internally. An external Pull-Up Resistor ($R_L$) is connected between the common wire and $V_{CC}$.
• If any transistor turns ON, it pulls the line to Ground. The line only rises to $V_{CC}$ when all open-collector transistors are turned OFF.

2.3 Comparison Table: Totem-Pole Output vs. Open Collector Output

Feature	Totem-Pole Output	Open Collector Output
Output Components	Active pull-up ($T_4$ + Diode $D$) and active pull-down ($T_3$).	Only active pull-down ($T_3$); collector of $T_3$ is left open.
External Resistor	Not required.	MUST use an external pull-up resistor ($R_L$) to $V_{CC}$.
Tying Outputs Directly	Forbidden (causes destructive short-circuit currents).	Allowed (creates a common bus using wired-AND logic).
Switching Speed	Fast (active pull-up transistor charges load capacitance quickly).	Slow (RC time constant of $R_L$ and load capacitance limits rise time).
Power Dissipation	Low when idle.	High when output is LOW (continuous current flows through $R_L$ to Ground).
Wired-AND Capability	No.	Yes.

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3. Wired-AND Logic

graph LR
    Gate1[NAND Gate 1 Output] & Gate2[NAND Gate 2 Output] --> TiedNode[Common Tied Node Y]
    TiedNode --> PullUp[External Pull-up Resistor RL to VCC]
    TiedNode --> Function[Function: Y = AB ' • CD ']

Major Exam Proof: Wired-AND Justification (2015 - 11 Marks)

Statement: “Open collector TTL gates tied together form a Wired-AND logic.”

Proof:

1. If Gate 1 outputs LOW, its $T_3$ pulls node $Y$ to Ground, regardless of Gate 2.
2. If Gate 2 outputs LOW, its $T_3$ pulls node $Y$ to Ground, regardless of Gate 1.
3. Node $Y$ is HIGH only if BOTH Gate 1 AND Gate 2 outputs are HIGH.
4. Mathematical function: $Y=(AB{)}^{\prime }\cdot (CD{)}^{\prime }=(AB+CD{)}^{\prime }\text{(AND-OR-INVERT Logic)}■$

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Past Year Questions (PYQs)

• [PYQ 2015]: Wired-AND logic justification for open collector gates. (11 Marks)
• [PYQ 2019]: Common bus system operation using open collector gates. (07 Marks)
• [PYQ 2023]: TTL AND gate operation and truth table. (09 Marks)
• [PYQ 2025]: TTL NAND gate working principle and circuit schematic. (08 Marks)

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Related Concepts: 03 BJT as NOT Gate & Inverter Operation | 04 Diode Logic & DTL Logic Families | 05 TTL Logic Families & Open Collector Bus Systems

4.06 CMOS Logic & Logic Gate Characteristics

Concept Overview: CMOS & Bipolar Families

CMOS (Complementary Metal-Oxide Semiconductor) uses complementary pairs of p-channel (PMOS) and n-channel (NMOS) MOSFETs. It is the dominant VLSI logic family due to its near-zero static power consumption and extremely high integration density.

Beyond MOS logic, specialized bipolar logic families like ECL (Emitter-Coupled Logic) operate in non-saturating states to achieve maximum switching speeds.

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1. 3-Input CMOS NAND Gate Operation [PYQ 2019]

Major PYQ Problem: 3-Input CMOS NAND Circuit (2019 - 5 Marks)

Rule of Thumb: CMOS NAND = PMOS in Parallel (PUN), NMOS in Series (PDN).

Circuit Construction & Operation:

• Pull-Up Network (PUN): Three PMOS transistors ($P_A,P_B,P_C$) connected in parallel between $V_{DD}$ and Output $Y$.
• Pull-Down Network (PDN): Three NMOS transistors ($N_A,N_B,N_C$) connected in series between Output $Y$ and Ground.

graph TD
    subgraph CMOS 3-Input NAND Network Architecture
        VDD[Power Supply VDD] --> PUN[Pull-Up Network: 3 PMOS Transistors in PARALLEL]
        PUN --> OutY[Output Node Y]
        OutY --> PDN[Pull-Down Network: 3 NMOS Transistors in SERIES]
        PDN --> GND[Ground VSS]
    end

Operational Truth:

• If ANY Input ($A,B,C$) is LOW (0V): At least one PMOS turns ON, connecting $Y$ to $V_{DD}$. At least one NMOS in the series stack turns OFF, breaking the path to Ground. Output $Y=\text{HIGH}$ ($V_{DD}$).
• If ALL Inputs ($A,B,C$) are HIGH (5V): All three PMOS turn OFF. All three NMOS turn ON, creating a continuous path from $Y$ to Ground. Output $Y=\text{LOW}$ ($0\text{V}$).

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2. 3-Input CMOS NOR Gate Operation

Concept: CMOS NOR Rules

Rule of Thumb: CMOS NOR = PMOS in Series (PUN), NMOS in Parallel (PDN).

Circuit Construction & Operation:

• Pull-Up Network (PUN): Three PMOS transistors ($P_A,P_B,P_C$) connected in series between $V_{DD}$ and Output $Y$.
• Pull-Down Network (PDN): Three NMOS transistors ($N_A,N_B,N_C$) connected in parallel between Output $Y$ and Ground.

graph TD
    subgraph CMOS 3-Input NOR Network Architecture
        VDD[Power Supply VDD] --> PUN[Pull-Up Network: 3 PMOS Transistors in SERIES]
        PUN --> OutY[Output Node Y]
        OutY --> PDN[Pull-Down Network: 3 NMOS Transistors in PARALLEL]
        PDN --> GND[Ground VSS]
    end

Operational Truth:

• If ANY Input ($A,B,C$) is HIGH (5V): At least one NMOS turns ON, connecting Output $Y$ to Ground. At least one series PMOS turns OFF, disconnecting the path to $V_{DD}$. Output $Y=\text{LOW}$ ($0\text{V}$).
• If ALL Inputs ($A,B,C$) are LOW (0V): All three PMOS turn ON, creating a continuous path from $V_{DD}$ to Output $Y$. All three NMOS turn OFF, breaking all paths to Ground. Output $Y=\text{HIGH}$ ($V_{DD}$).

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3. Emitter-Coupled Logic (ECL) OR/NOR Gate Operation [Syllabus Week 8]

Foundational Concept (Outside Direct PYQ Scope)

Emitter-Coupled Logic (ECL) represents the pinnacle of high-speed silicon bipolar logic technology. While its non-saturating switching principles are essential digital foundations, detailed ECL circuit design calculations and schematics have never appeared in ECE 2103 past year question papers.

Emitter-Coupled Logic (ECL) is a non-saturating bipolar transistor logic family. By keeping the transistors out of the saturation region (operating strictly in the active and cut-off regions), it completely eliminates carrier storage time delays, making ECL the fastest semiconductor logic family (with sub-nanosecond propagation delays $<1\text{ ns}$).

Circuit Configuration & Logic Steering:

• Uses a differential amplifier input stage. Two input transistors ($T_A,T_B$) have their emitters tied together to a common emitter resistor $R_E$ connected to a negative supply $V_{EE}=-5.2\text{V}$.
• A reference transistor ($T_{REF}$) has its base connected to a fixed internal reference voltage $V_{BB}$.
• The collector outputs feed into emitter followers ($T_{OUT1},T_{OUT2}$) which act as low-impedance buffers providing the OR and NOR outputs simultaneously.

graph TD
    subgraph ECL Logic Steering
        Inputs[Inputs A, B] --> DiffAmp[Differential Input Transistors TA, TB]
        VBB[Reference Voltage VBB] --> RefTrans[Reference Transistor T_REF]
        DiffAmp & RefTrans --> CurrentSource[Common Current Source to VEE]
        DiffAmp -->|Collector 1| NOR[NOR Emitter Follower Output]
        RefTrans -->|Collector 2| OR[OR Emitter Follower Output]
    end

Operation:

• Inputs LOW (Logic 0): The input transistors ($T_A,T_B$) are cut off. The current through $R_E$ is steered entirely through $T_{REF}$ because $V_{BB}$ is higher than the input voltage. This drops the collector voltage of $T_{REF}$, pulling the OR output LOW. The collector of $T_A,T_B$ remains high, keeping the NOR output HIGH.
• ANY Input HIGH (Logic 1): The corresponding input transistor ($T_A$ or $T_B$) turns ON, steering the emitter current away from $T_{REF}$ (which now turns OFF). The collector of $T_A,T_B$ drops, pulling the NOR output LOW. The collector of $T_{REF}$ rises, pulling the OR output HIGH.

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4. Core Four Logic Gate Characteristics

10-Mark Exam Definitions (2015, 2016, 2018, 2021, 2024, 2025)

1. Fan-out: The maximum number of standard logic inputs that a single gate’s output can reliably drive without causing output voltage degradation below noise thresholds. $\text{Fan-out}=\min \left(\frac{I_{OH}}{I_{IH}},\frac{I_{OL}}{I_{IL}}\right)$

2. Propagation Delay ($t_{pd}$): The average time delay required for a signal transition to propagate from gate input to gate output: $t_{pd}=\frac{t_{pHL}+t_{pLH}}{2}$

3. Noise Margin: The maximum external noise voltage that can be added to an input signal without triggering an unintended change in output logic state: $\text{High Noise Margin: }N{M}_H=V_{OH(min)}-V_{IH(min)}$ $\text{Low Noise Margin: }N{M}_L=V_{IL(max)}-V_{OL(max)}$

4. Power Dissipation: The total electrical power consumed by a logic gate during operation, expressed in milliwatts (mW).

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5. Current Sourcing vs. Current Sinking

graph LR
    subgraph Current Sourcing HIGH Output
        Driver1[Driver Gate Output HIGH] -->|Sources Current IOH out of pin| Load1[Load Gate Inputs]
    end
    
    subgraph Current Sinking LOW Output
        Load2[Load Gate Inputs] -->|Sinks Current IOL into pin| Driver2[Driver Gate Output LOW to GND]
    end

• Current Sourcing ($I_{OH}$): Driver gate output is HIGH (Logic 1). Current flows out of driver output pin into load inputs.
• Current Sinking ($I_{OL}$): Driver gate output is LOW (Logic 0). Current flows from load inputs into driver output pin to Ground.

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6. Master Logic Family Comparison Table [Syllabus Week 8]

Parameter	Diode-Transistor Logic (DTL)	Transistor-Transistor Logic (TTL)	Emitter-Coupled Logic (ECL)	Complementary MOS (CMOS)
Basic Gate	NAND	NAND	OR / NOR	NAND / NOR
Transistor State	Saturating	Saturating	Non-Saturating (Active/Cut-off)	Enhancement (MOSFET)
Propagation Delay	Slow ($\approx 30\text{ ns}$)	Medium ($\approx 10\text{ ns}$)	Extremely Fast ($<1\text{ ns}$)	Medium-to-Fast ($1.5\to 15\text{ ns}$)
Power Dissipation	Medium ($\approx 12\text{ mW}$)	Medium ($\approx 10\text{ mW}$)	High ($\approx 25\text{ mW}$)	Extremely Low (near 0 static power)
Noise Margin	Medium ($\approx 0.7\text{V}$)	Medium ($\approx 0.4\text{V}$)	Low ($\approx 0.25\text{V}$)	High ($1.5\text{V}$ or $30\%$ of $V_{DD}$)
Fan-out	Low ($\approx 8$)	Medium ($\approx 10$)	High ($\approx 25$)	Very High ($>50$)

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7. Past Year Questions (PYQs)

• [PYQ 2019]: Draw 3-input CMOS NAND gate circuit and explain operation. (05 Marks)
• [PYQ 2016, 2018, 2021, 2024, 2025]: Define Fan-out, Propagation delay, Noise margin, Power dissipation, Current Sourcing. (08 to 10 Marks)

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Related Concepts: 01 Digital Systems & Signal Propagation | 02 Universal Logic Gates & 2-Level Implementations | 06 CMOS Logic & Logic Gate Characteristics

4.07 Logic Analysis, Switching Circuits & Positive-Negative Logic

Advanced Physical Logic Concepts

Analyzing physical digital circuits requires converting hardware voltage states or physical mechanical switches into formal Boolean algebraic notation.

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1. Positive & Negative Logic Systems

In hardware, binary values (1 and 0) are assigned to voltage levels ($V_H$ and $V_L$):

• Positive Logic System: High Voltage $V_H=1$, Low Voltage $V_L=0$.
• Negative Logic System: High Voltage $V_H=0$, Low Voltage $V_L=1$.

Major Exam Proof: Positive AND = Negative OR (2015, 2019, 2023, 2025 - 11 Marks)

Question: Prove mathematically that a Positive-Logic AND gate is a Negative-Logic OR gate and vice-versa.

Proof Solution:

Step 1: Physical Voltage Truth Table

Consider a hardware gate that outputs High voltage ($H$) ONLY when both inputs are High ($H$):

Input X	Input Y	Output Z
$L$	$L$	$L$
$L$	$H$	$L$
$H$	$L$	$L$
$H$	$H$	$H$

Step 2: Positive Logic Assignment ($H=1,L=0$)

Substituting $H=1,L=0$: $\text{Table: }(0,0\to 0),(0,1\to 0),(1,0\to 0),(1,1\to 1)⟹\mathbf{Z}=\mathbf{X}\cdot \mathbf{Y}(\text{AND Gate})$

Step 3: Negative Logic Assignment ($H=0,L=1$)

Substituting $H=0,L=1$: $\text{Table: }(1,1\to 1),(1,0\to 1),(0,1\to 1),(0,0\to 0)⟹\mathbf{Z}=\mathbf{X}+\mathbf{Y}(\text{OR Gate})$

$\therefore \text{Positive-Logic AND Gate}\equiv \text{Negative-Logic OR Gate}■$

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2. Physical Switching Circuit Translation Rules

Major Exam Switch Puzzle (2024, 2025 - 7 Marks)

graph TD
    Switch[Physical Mechanical Switches] --> Series[Series Connection: Switch A and B end-to-end]
    Switch --> Parallel[Parallel Connection: Switch A and B side-by-side]
    Switch --> NC[Normally-Closed Contact]
    
    Series --> AND[Boolean AND Logic: A • B]
    Parallel --> OR[Boolean OR Logic: A + B]
    NC --> NOT[Boolean Inversion: A']

Golden Rules:

1. Series Switches: Forms AND ($\cdot$) logic. Current flows if both switches are closed.
2. Parallel Switches: Forms OR ($+$) logic. Current flows if either switch is closed.
3. Normally-Closed Contact: Forms NOT (${}^{\prime }$) logic. Opening switch breaks circuit.

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3. Formal Multi-Level Intermediate Variable Analysis (Morris Mano Method)

Multi-Level Analysis Algorithm (2016, 2019 - 12 Marks)

1. Label Level 1 Outputs: Assign intermediate variable symbols ($T_1,T_2$) to outputs of gates driven purely by primary inputs.
2. Label Level 2 Outputs: Assign symbols ($T_3,T_4$) to subsequent level gate outputs driven by $T_1,T_2$.
3. Sequential Substitution: Express $T_3=f(T_1,T_2)$, then substitute original input variables ($A,B,C$) backwards to derive output $F$.

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4. PYQ Master Methodology: Circuit Analysis to Single Gate

PYQ Note (2023): Circuit Analysis to Single Gate

When an exam question provides a drawn logic circuit (e.g. Fig 2c in 2023) and asks to “extract the Boolean expression and reduce to a single logic gate”:

1. Assign intermediate variables ($T_1,T_2$) to the outputs of the first level of gates.
2. Cascade the equations forward until you derive the unsimplified output expression.
3. Apply Boolean algebra simplification. The resulting algebraic expression will always factor down into either an XOR ($A\oplus B=A^{\prime }B+A{B}^{\prime }$) or an XNOR ($A\odot B=AB+A^{\prime }{B}^{\prime }$) expression, allowing implementation via a single gate! $■$

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Past Year Questions (PYQs)

• [PYQ 2015, 2019, 2023, 2025]: Positive-logic AND = Negative-logic OR proof. (11 Marks)
• [PYQ 2024, 2025]: Express switching circuit diagram into binary logic expression. (07 Marks)
• [PYQ 2016, 2019]: Multi-level logic circuit analysis using intermediate variables. (12 Marks)
• [PYQ 2023]: Analyze drawn circuit diagram and reduce to a single logic gate. (08 Marks)

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