04 Chapter 4 - Universal Gates & Advanced Logic Families (Merged)

Chapter 4: Universal Gates & Advanced Logic Families - Complete Study Notes

NotebookLM Ingestion Compilation

This merged document contains all 7 study notes for Chapter 4: Universal Gates & Advanced Logic Families from ECE 2103 Digital Electronics (Sharif Sir).

---

Related Concepts: 02 Universal Logic Gates & 2-Level Implementations | 03 BJT as NOT Gate & Inverter Operation | 06 CMOS Logic & Logic Gate Characteristics

4.01 Digital Systems & Signal Propagation

What is a Digital System?

A Digital System is an electronic system that processes, stores, and transmits information represented in discrete binary states {typically logic 0 (0V) and logic 1 (5V or 3.3V)}, as opposed to Analog Systems which process continuous physical quantities.

graph TD
    subgraph Digital Advantages
        D[Digital System Benefits] --> A1[1. Superior Noise Immunity]
        D --> A2[2. Ease of Programmability]
        D --> A3[3. High Scalability & IC Integration]
        D --> A4[4. Exact Reproduction & Storage]
    end

    subgraph Signal Transmission Channel Model
        Tx[Transmitter: Ideal Digital Pulse] --> Channel[Transmission Channel / PCB Trace]
        Channel -->|Attenuation & Parasitic Capacitance| Degradation[Degraded Signal: Lowers Amplitude & Rounds Edges]
        Degradation --> Rx[Receiver Gate: Needs Noise Margin]
    end

---

1. Nine Engineering Advantages of Digital Systems

1. Superior Noise Immunity: Discrete threshold levels make digital signals far less susceptible to external noise corruption than continuous analog signals.
2. Ease of Programmability: System operations are dictated by software and firmware code rather than fixed hardware modifications.
3. High Integration Density (VLSI): Millions of transistors can be fabricated onto a single silicon die.
4. Exact Signal Reproduction & Storage: Binary data can be stored permanently in RAM/Flash without quality degradation.
5. Enhanced Security & Cryptography: Binary streams are easily encrypted using digital ciphers {e.g., XOR masks}.
6. Cost-Effective Mass Production: Standardized CMOS fabrication reduces per-gate costs.
7. Simplified System Design: Modular logic gate building blocks eliminate complex analog bias calculations.
8. High Reliability & Precision: Output precision is increased simply by increasing bit-width.
9. Direct Compatibility with Microprocessors: Native binary alignment with CPUs and digital signal processors (DSPs).

---

2. Signal Propagation & Physical Distortion

When a digital pulse travels across a transmission line or PCB copper trace, it experiences physical degradation due to channel parasitics:

• Attenuation: The gradual reduction in voltage amplitude caused by trace resistance.
• Phase Shift / Dispersion: Propagation delay differences across frequency components, causing pulse rounding and inter-symbol interference (ISI).

---

Past Year Questions (PYQs)

• [PYQ 2020, 2024, 2025]: Advantages of digital systems over analog systems. (07 to 10 Marks)
• [Class Test Q&A]: Describe signal propagation phenomena and transmission line degradation.

---

Related Concepts: 01 Digital Systems & Signal Propagation | 03 BJT as NOT Gate & Inverter Operation | 05 TTL Logic Families & Open Collector Bus Systems

4.02 Universal Logic Gates & 2-Level Implementations

What is a Universal Logic Gate?

A logic gate is classified as Universal if any arbitrary Boolean function or digital circuit can be constructed using only that single gate type, without requiring any other gate types.

Both NAND and NOR gates are Universal Gates.

graph TD
    subgraph 4-NAND Gate XOR Network
        InA[Input A] & InB[Input B] --> NAND1[NAND 1: Output N1 = AB']
        InA & NAND1 --> NAND2[NAND 2: Output N2 = A • N1 ']
        InB & NAND1 --> NAND3[NAND 3: Output N3 = B • N1 ']
        NAND2 & NAND3 --> NAND4[NAND 4: Output F = A ⊕ B]
    end

---

1. NAND & NOR Gate Realizations of Basic Gates

Target Gate	NAND Gates Required	NOR Gates Required
NOT	1 (inputs tied: $\overline{A\cdot A}=A^{\prime }$)	1 (inputs tied: $\overline{A+A}=A^{\prime }$)
AND	2 ($\overline{\overline{AB}}=AB$)	3 ($\overline{A^{\prime }+B^{\prime }}=AB$)
OR	3 ($\overline{A^{\prime }\cdot B^{\prime }}=A+B$)	2 ($\overline{\overline{A+B}}=A+B$)
XOR	4 (cascaded 4-NAND network)	5 (4-NOR XNOR + 1 NOR Inverter)
XNOR	5 (4-NAND XOR + 1 NAND Inverter)	4 (cascaded 4-NOR network)

---

2. Two-Level Gate Implementation Rules

A. Two-Level NAND-NAND Implementation (SOP)

• Rule: Any function in Sum of Products (SOP) form can be directly implemented using a 2-level NAND-NAND circuit.
• Proof: $F=AB+CD⟹F=((AB+CD{)}^{\prime }{)}^{\prime }=((AB{)}^{\prime }\cdot (CD{)}^{\prime }{)}^{\prime }$. This represents a final NAND gate taking inputs from two level-1 NAND gates.
• Direct Literals Rule: If a single literal (e.g., $E$) feeds directly into the second-level OR/NAND gate, it must be complemented ($E^{\prime }$) to cancel out the output gate’s inversion.

B. Two-Level NOR-NOR Implementation (POS)

• Rule: Any function in Product of Sums (POS) form can be directly implemented using a 2-level NOR-NOR circuit.
• Proof: $F=(A+B)(C+D)⟹F=(((A+B)(C+D){)}^{\prime }{)}^{\prime }=((A+B{)}^{\prime }+(C+D{)}^{\prime }{)}^{\prime }$. This represents a final NOR gate taking inputs from two level-1 NOR gates.

---

3. Major Exam Proofs

Major PYQ Proof: 5-Gate NOR XOR Circuit (2015, 2021 - 8 Marks)

Question: Show mathematically that a 5-gate NOR network acts as an Exclusive-OR (XOR) gate.

Proof Solution:

1. $N_1=\overline{A+B}$
2. $N_2=\overline{A+N_1}=\overline{A+(A+B{)}^{\prime }}=\overline{A+A^{\prime }{B}^{\prime }}=A^{\prime }\cdot (A+B)=A^{\prime }B$
3. $N_3=\overline{B+N_1}=\overline{B+(A+B{)}^{\prime }}=\overline{B+A^{\prime }{B}^{\prime }}=B^{\prime }\cdot (A+B)=A{B}^{\prime }$
4. $N_4=\overline{N_2+N_3}=\overline{A^{\prime }B+A{B}^{\prime }}=A\odot B\text{(XNOR)}$
5. $N_5=\overline{N_4}=\overline{A\odot B}=\mathbf{A}\oplus \mathbf{B}\text{(XOR)}■$

---

Limited Gate Puzzle: Implementation with $\le 2$ NOR Gates (2015, 2021 - 12 Marks)

Question: Minimize a function with don’t cares and implement it using no more than two NOR gates.

• Solution Strategy: When gate count is restricted to $\le 2$ NOR gates, group the $0$s in the K-map to find $F^{\prime }$. Taking the complement yields $F=(F^{\prime }{)}^{\prime }$. If $F^{\prime }$ simplifies to a single sum term {e.g., $F^{\prime }=A+B$}, then $F=(A+B{)}^{\prime }$, which is executed by a single NOR gate!

---

Past Year Questions (PYQs)

• [PYQ 2021]: Prove NOR is a universal gate with basic gate implementations. (08 Marks)
• [PYQ 2015, 2021]: 5-gate NOR XOR circuit proof. (08 Marks)
• [PYQ 2015, 2021]: Implement function with no more than two NOR gates. (12 Marks)

---

Related Concepts: 01 Digital Systems & Signal Propagation | 04 NPN Transistor Basics & DTL Logic | 05 TTL Logic Families & Open Collector Bus Systems

4.03 BJT as NOT Gate & Inverter Operation

BJT Transistor Switch Concept

In digital logic, a Bipolar Junction Transistor (BJT) operates strictly as a digital switch driven between two extreme operating states:

1. Cut-off Region (OFF Switch): Base-Emitter junction reverse-biased $⟹I_B=0,I_C=0,V_{out}=V_{CC}$ (Logic HIGH).
2. Saturation Region (ON Switch): Base-Emitter junction forward-biased $⟹I_B\ge I_{B(sat)},V_{out}=V_{CE(sat)}\approx 0.2\text{V}$ (Logic LOW).

graph TD
    Input[Input Voltage Vin] --> Check{Vin Level}
    
    Check -->|Vin = LOW e.g. 0.2V| Cutoff[Cut-off Region: BE Junction OFF]
    Cutoff --> ICZero[Collector Current IC = 0]
    ICZero --> OutHigh[Output Vout = VCC = HIGH Logic 1]
    
    Check -->|Vin = HIGH e.g. 5V| Saturation[Saturation Region: BE Junction ON]
    Saturation --> ICSat[Max Collector Current IC-sat]
    ICSat --> OutLow[Output Vout = VCE-sat = 0.2V = LOW Logic 0]

---

1. Mathematical Saturation & Cut-off Proof

Major Exam Numerical Problem (2016, 2019 - 13 Marks)

Given Circuit Parameters:

• $V_{CC}=5\text{V}$, $V_{in(HIGH)}=5\text{V}$, $V_{in(LOW)}=0.2\text{V}$
• Base Resistor $R_B=10\text{k}\Omega$, Collector Resistor $R_C=1\text{k}\Omega$
• Minimum Current Gain $h_{FE}(\beta )=30$
• Transistor Constants: $V_{BE(sat)}=0.7\text{V}$, $V_{CE(sat)}=0.2\text{V}$

Part A: Operation when $V_{in}=0.2\text{V}$ (Logic LOW)

1. Base-Emitter voltage $V_{BE}=0.2\text{V}<0.7\text{V}$ {below cut-in threshold}.
2. Transistor is in Cut-off. Base current $I_B=0$, Collector current $I_C=0$.
3. Output voltage: $V_{out}=V_{CC}-(I_C\cdot R_C)=5\text{V}-(0\cdot 1\text{k}\Omega )=5\text{V}(\text{Logic HIGH})$

---

Part B: Operation when $V_{in}=5\text{V}$ (Logic HIGH)

1. Calculate actual base current ($I_B$): $I_B=\frac{V_{in}-V_{BE(sat)}}{R_B}=\frac{5\text{V}-0.7\text{V}}{10\text{k}\Omega }=\frac{4.3\text{V}}{10\text{k}\Omega }=0.43\text{ mA}$

2. Calculate saturation collector current ($I_{C(sat)}$): $I_{C(sat)}=\frac{V_{CC}-V_{CE(sat)}}{R_C}=\frac{5\text{V}-0.2\text{V}}{1\text{k}\Omega }=\frac{4.8\text{V}}{1\text{k}\Omega }=4.8\text{ mA}$

3. Calculate minimum base current required for saturation ($I_{B(min)}$): $I_{B(min)}=\frac{I_{C(sat)}}{h_{FE}}=\frac{4.8\text{ mA}}{30}=0.16\text{ mA}$

4. Saturation Condition Check: $I_B(0.43\text{ mA})\ge I_{B(min)}(0.16\text{ mA})$ Since $I_B>I_{B(min)}$, the transistor is driven deep into saturation.

5. Output voltage drops to saturation voltage: $V_{out}=V_{CE(sat)}=0.2\text{V}(\text{Logic LOW})■$

---

Past Year Questions (PYQs)

• [PYQ 2016, 2019]: BJT inverter operation: Mathematical proof of saturation/cut-off given circuit parameters. (13 Marks)

---

Related Concepts: 03 BJT as NOT Gate & Inverter Operation | 05 TTL Logic Families & Open Collector Bus Systems | 06 CMOS Logic & Logic Gate Characteristics

4.04 NPN Transistor Basics & DTL Logic

Physical Hardware of Logic

Before analyzing complex integrated logic families like TTL, understanding the current-voltage ($I-V$) characteristics of an NPN Bipolar Junction Transistor (BJT) and its application in Diode-Transistor Logic (DTL) is required.

---

1. NPN Silicon Transistor Characteristic Curves

A. Base Input Characteristics ($I_B$ vs. $V_{BE}$)

• Curve Behavior: Operates like a forward-biased PN junction diode.
• Key Voltage: Negligible base current flows until $V_{BE}$ reaches cut-in voltage ($\approx 0.6\text{V}$). In saturation, $V_{BE(sat)}\approx 0.7\text{V}-0.8\text{V}$.

B. Collector Output Characteristics ($I_C$ vs. $V_{CE}$)

Divided into three distinct regions:

1. Cut-off Region: $I_B=0⟹I_C\approx 0,V_{CE}\approx V_{CC}$ (OFF Switch).
2. Active Region: Linear amplification region (not used in digital logic).
3. Saturation Region: $V_{CE}$ drops to $V_{CE(sat)}\approx 0.2\text{V}$, $I_C$ reaches maximum limit $I_{C(sat)}$ (ON Switch).

---

2. DTL NAND Gate Saturation Proof

Major PYQ Proof: DTL Gate Saturation ( $h_{FE}=20$) (2021, 2022 - 10 Marks)

Given DTL NAND Parameters:

• $V_{CC}=5\text{V}$, $R_1=5\text{k}\Omega$, $R_2=5\text{k}\Omega$, $R_C=2\text{k}\Omega$, $h_{FE}=20$
• Diode drop $V_D=0.7\text{V}$, $V_{BE(sat)}=0.8\text{V}$, $V_{CE(sat)}=0.2\text{V}$

Proof Steps:

1. Input State: All inputs ($A,B,C$) are HIGH ($5\text{V}$) $⟹$ Input diodes are reverse-biased (OFF).

2. Node Voltage $V_P$ (Anode of level-shift diode $D_1$): $V_P=V_{D1}+V_{D2}+V_{BE(sat)}=0.7\text{V}+0.7\text{V}+0.8\text{V}=2.2\text{V}$

3. Current Calculations:

   • Current from $V_{CC}$ through $R_1$: $I_1=\frac{V_{CC}-V_P}{R_1}=\frac{5\text{V}-2.2\text{V}}{5\text{k}\Omega }=0.56\text{ mA}$
   • Current lost to ground through $R_2$: $I_2=\frac{V_{BE(sat)}}{R_2}=\frac{0.8\text{V}}{5\text{k}\Omega }=0.16\text{ mA}$
   • Base current entering transistor ($I_B$): $I_B=I_1-I_2=0.56\text{ mA}-0.16\text{ mA}=0.40\text{ mA}$

4. Saturation Check:

   • Maximum saturation collector current ($I_{C(sat)}$): $I_{C(sat)}=\frac{V_{CC}-V_{CE(sat)}}{R_C}=\frac{5\text{V}-0.2\text{V}}{2\text{k}\Omega }=2.4\text{ mA}$
   • Available collector current drive: $h_{FE}\times I_B=20\times 0.40\text{ mA}=8.0\text{ mA}$

5. Since $8.0\text{ mA}\gg 2.4\text{ mA}$ ($h_{FE}{I}_B\ge I_{C(sat)}$), the output transistor is driven deep into saturation. $■$

---

Past Year Questions (PYQs)

• [PYQ 2022]: Draw and explain Transistor Base and Collector characteristics. (09 Marks)
• [PYQ 2021, 2022]: DTL gate output transistor saturation proof ($h_{FE}=20$). (10 Marks)

---

Related Concepts: 03 BJT as NOT Gate & Inverter Operation | 04 NPN Transistor Basics & DTL Logic | 06 CMOS Logic & Logic Gate Characteristics

4.05 TTL Logic Families & Open Collector Bus Systems

Concept Overview: TTL Logic

Transistor-Transistor Logic (TTL) replaced DTL by utilizing multi-emitter transistors at the input stage, achieving much higher switching speeds.

Standard TTL uses a Totem-Pole output for active pull-up and pull-down. Open-Collector TTL removes the active pull-up to allow outputs to be safely tied together for common bus systems.

graph TD
    subgraph TTL NAND Totem-Pole Stages
        InputStage[Input Stage: Multi-Emitter Transistor T1] --> PhaseSplitter[Phase Splitter: Transistor T2]
        PhaseSplitter -->|Inverted Collector Output| PullUp[Active Pull-Up: Transistor T4 + Diode D]
        PhaseSplitter -->|Direct Emitter Output| PullDown[Active Pull-Down: Transistor T3]
        PullUp & PullDown --> OutputNode[Output Y]
    end

---

1. Standard TTL NAND Gate Working Principle

• Inputs: Multi-emitter transistor $T_1$.

• Case 1: ANY Input is LOW (0V)

  • Emitter-base junction of $T_1$ is forward-biased $⟹$ current flows out of input pin.
  • Base-collector junction of $T_1$ is reverse-biased $⟹T_2$ turns OFF.
  • $T_2$ OFF $⟹$ pull-down transistor $T_3$ turns OFF.
  • Collector of $T_2$ rises toward $V_{CC}$, driving base of $T_4⟹$ pull-up transistor $T_4$ turns ON.
  • Result: Output pulled HIGH to $V_{CC}$ ($Y=1$).

• Case 2: ALL Inputs are HIGH (5V)

  • Emitter-base junctions of $T_1$ are reverse-biased.
  • Base-collector junction of $T_1$ becomes forward-biased, steering base current into $T_2⟹T_2$ turns ON.
  • $T_2$ ON $⟹$ emitter current drives $T_3$ ON into deep saturation.
  • Collector of $T_2$ drops low $⟹$ pull-up transistor $T_4$ turns OFF (diode $D$ ensures $T_4$ stays OFF).
  • Result: Output pulled LOW to Ground through $T_3$ ($Y=0$).

---

2. Open Collector Gates & Wired-AND Logic

Connecting standard Totem-Pole outputs directly together causes destructive short-circuit currents when one gate outputs HIGH while another outputs LOW.

Open Collector TTL Solution:

• The active pull-up transistor ($T_4$) and diode ($D$) are removed.
• The collector of $T_3$ is left unconnected internally. An external Pull-Up Resistor ($R_L$) is attached between the node and $V_{CC}$.

graph LR
    Gate1[NAND Gate 1 Output] & Gate2[NAND Gate 2 Output] --> TiedNode[Common Tied Node Y]
    TiedNode --> PullUp[External Pull-up Resistor RL to VCC]
    TiedNode --> Function[Function: Y = AB ' • CD ']

Major Exam Proof: Wired-AND Justification (2015 - 11 Marks)

Statement: “Open collector TTL gates tied together form a Wired-AND logic.”

Proof:

1. If Gate 1 outputs LOW, its $T_3$ pulls node $Y$ to Ground, regardless of Gate 2.
2. If Gate 2 outputs LOW, its $T_3$ pulls node $Y$ to Ground, regardless of Gate 1.
3. Node $Y$ is HIGH only if BOTH Gate 1 AND Gate 2 outputs are HIGH.
4. Mathematical function: $Y=(AB{)}^{\prime }\cdot (CD{)}^{\prime }=(AB+CD{)}^{\prime }\text{(AND-OR-INVERT Logic)}■$

---

Past Year Questions (PYQs)

• [PYQ 2015]: Wired-AND logic justification for open collector gates. (11 Marks)
• [PYQ 2019]: Common bus system operation using open collector gates. (07 Marks)
• [PYQ 2023]: TTL AND gate operation and truth table. (09 Marks)
• [PYQ 2025]: TTL NAND gate working principle and circuit schematic. (08 Marks)

---

Related Concepts: 03 Logic Gate Characteristics & Buffer Gates | 04 NPN Transistor Basics & DTL Logic | 05 TTL Logic Families & Open Collector Bus Systems

4.06 CMOS Logic & Logic Gate Characteristics

Concept Overview: CMOS & Specialized Bipolar Families

CMOS (Complementary Metal-Oxide Semiconductor) uses complementary pairs of p-channel (PMOS) and n-channel (NMOS) MOSFETs. It is the dominant VLSI logic family due to its near-zero static power consumption and extremely high integration density.

graph TD
    subgraph CMOS 3-Input NAND Network Architecture
        VDD[Power Supply VDD] --> PUN[Pull-Up Network: 3 PMOS Transistors in PARALLEL]
        PUN --> OutY[Output Node Y]
        OutY --> PDN[Pull-Down Network: 3 NMOS Transistors in SERIES]
        PDN --> GND[Ground VSS]
    end

---

1. 3-Input CMOS NAND Gate Operation

Major PYQ Problem: 3-Input CMOS NAND Circuit (2019 - 5 Marks)

Rule of Thumb: CMOS NAND = PMOS in Parallel (PUN), NMOS in Series (PDN).

Circuit Construction & Operation:

• Pull-Up Network (PUN): Three PMOS transistors ($P_A,P_B,P_C$) connected in parallel between $V_{DD}$ and Output $Y$.
• Pull-Down Network (PDN): Three NMOS transistors ($N_A,N_B,N_C$) connected in series between Output $Y$ and Ground.

Operational Truth:

• If ANY Input ($A,B,C$) is LOW (0V): At least one PMOS turns ON, connecting $Y$ to $V_{DD}$. At least one NMOS in the series stack turns OFF, breaking the path to Ground. Output $Y=\text{HIGH}$ ($V_{DD}$).
• If ALL Inputs ($A,B,C$) is HIGH (5V): All three PMOS turn OFF. All three NMOS turn ON, creating a continuous path from $Y$ to Ground. Output $Y=\text{LOW}$ ($0\text{V}$).

---

2. Core Four Logic Gate Characteristics

10-Mark Exam Definitions (2015, 2016, 2018, 2021, 2024, 2025)

1. Fan-out: The maximum number of standard logic inputs that a single gate’s output can reliably drive without causing output voltage degradation below noise thresholds. $\text{Fan-out}=\min \left(\frac{I_{OH}}{I_{IH}},\frac{I_{OL}}{I_{IL}}\right)$

2. Propagation Delay ($t_p$): The average time delay required for a signal transition to propagate from gate input to gate output: $t_p=\frac{t_{pHL}+t_{pLH}}{2}$

3. Noise Margin: The maximum external noise voltage that can be added to an input signal without triggering an unintended change in output logic state: $\text{High Noise Margin: }N{M}_H=V_{OH(min)}-V_{IH(min)}$ $\text{Low Noise Margin: }N{M}_L=V_{IL(max)}-V_{OL(max)}$

4. Power Dissipation: The total electrical power consumed by a logic gate during operation, expressed in milliwatts (mW).

---

3. Current Sourcing vs. Current Sinking

graph LR
    subgraph Current Sourcing HIGH Output
        Driver1[Driver Gate Output HIGH] -->|Sources Current IOH out of pin| Load1[Load Gate Inputs]
    end
    
    subgraph Current Sinking LOW Output
        Load2[Load Gate Inputs] -->|Sinks Current IOL into pin| Driver2[Driver Gate Output LOW to GND]
    end

• Current Sourcing ($I_{OH}$): Driver gate output is HIGH (Logic 1). Current flows out of driver output pin into load inputs.
• Current Sinking ($I_{OL}$): Driver gate output is LOW (Logic 0). Current flows from load inputs into driver output pin to Ground.

---

4. Overview of Specialized Bipolar Families (ECL & I²L)

Syllabus Topic Overview: ECL & I²L Logic

Beyond TTL and CMOS, two specialized bipolar logic families exist in the theoretical syllabus:

• ECL (Emitter-Coupled Logic): A non-saturating bipolar logic family based on differential amplifiers. Because transistors are kept strictly out of saturation, ECL completely eliminates carrier storage delay, achieving sub-nanosecond propagation delays ($<1\text{ ns}$). It operates with negative supply voltages ($V_{EE}=-5.2\text{V}$) and has high power dissipation.
• I²L (Integrated Injection Logic): A high-density merged-transistor bipolar family that uses PNP current injectors and multi-collector NPN transistors. It operates at very low current levels, making it historically popular for dense bipolar microcircuits.

---

Past Year Questions (PYQs)

• [PYQ 2019]: Draw 3-input CMOS NAND gate circuit and explain operation. (05 Marks)
• [PYQ 2016, 2018, 2021, 2024, 2025]: Define Fan-out, Propagation delay, Noise margin, Power dissipation, Current Sourcing. (08 to 10 Marks)

---

Related Concepts: 01 Digital Systems & Signal Propagation | 02 Universal Logic Gates & 2-Level Implementations | 06 CMOS Logic & Logic Gate Characteristics

4.07 Logic Analysis, Switching Circuits & Positive-Negative Logic

Advanced Physical Logic Concepts

Analyzing physical digital circuits requires converting hardware voltage states or physical mechanical switches into formal Boolean algebraic notation.

---

1. Positive & Negative Logic Systems

In hardware, binary values (1 and 0) are assigned to voltage levels ($V_H$ and $V_L$):

• Positive Logic System: High Voltage $V_H=1$, Low Voltage $V_L=0$.
• Negative Logic System: High Voltage $V_H=0$, Low Voltage $V_L=1$.

Major Exam Proof: Positive AND = Negative OR (2015, 2019, 2023, 2025 - 11 Marks)

Question: Prove mathematically that a Positive-Logic AND gate is a Negative-Logic OR gate and vice-versa.

Proof Solution:

Step 1: Physical Voltage Truth Table

Consider a hardware gate that outputs High voltage ($H$) ONLY when both inputs are High ($H$):

Input X	Input Y	Output Z
$L$	$L$	$L$
$L$	$H$	$L$
$H$	$L$	$L$
$H$	$H$	$H$

Step 2: Positive Logic Assignment ($H=1,L=0$)

Substituting $H=1,L=0$: $\text{Table: }(0,0\to 0),(0,1\to 0),(1,0\to 0),(1,1\to 1)⟹\mathbf{Z}=\mathbf{X}\cdot \mathbf{Y}(\text{AND Gate})$

Step 3: Negative Logic Assignment ($H=0,L=1$)

Substituting $H=0,L=1$: $\text{Table: }(1,1\to 1),(1,0\to 1),(0,1\to 1),(0,0\to 0)⟹\mathbf{Z}=\mathbf{X}+\mathbf{Y}(\text{OR Gate})$

$\therefore \text{Positive-Logic AND Gate}\equiv \text{Negative-Logic OR Gate}■$

---

2. Physical Switching Circuit Translation Rules

Major Exam Switch Puzzle (2024, 2025 - 7 Marks)

graph TD
    Switch[Physical Mechanical Switches] --> Series[Series Connection: Switch A and B end-to-end]
    Switch --> Parallel[Parallel Connection: Switch A and B side-by-side]
    Switch --> NC[Normally-Closed Contact]
    
    Series --> AND[Boolean AND Logic: A • B]
    Parallel --> OR[Boolean OR Logic: A + B]
    NC --> NOT[Boolean Inversion: A']

Golden Rules:

1. Series Switches: Forms AND ($\cdot$) logic. Current flows if both switches are closed.
2. Parallel Switches: Forms OR ($+$) logic. Current flows if either switch is closed.
3. Normally-Closed Contact: Forms NOT (${}^{\prime }$) logic. Opening switch breaks circuit.

---

3. Formal Multi-Level Intermediate Variable Analysis (Morris Mano Method)

Multi-Level Analysis Algorithm (2016, 2019 - 12 Marks)

1. Label Level 1 Outputs: Assign intermediate variable symbols ($T_1,T_2$) to outputs of gates driven purely by primary inputs.
2. Label Level 2 Outputs: Assign symbols ($T_3,T_4$) to subsequent level gate outputs driven by $T_1,T_2$.
3. Sequential Substitution: Express $T_3=f(T_1,T_2)$, then substitute original input variables ($A,B,C$) backwards to derive output $F$.

---

Past Year Questions (PYQs)

• [PYQ 2015, 2019, 2023, 2025]: Positive-logic AND = Negative-logic OR proof. (11 Marks)
• [PYQ 2024, 2025]: Express switching circuit diagram into binary logic expression. (07 Marks)
• [PYQ 2016, 2019]: Multi-level logic circuit analysis using intermediate variables. (12 Marks)

---