Related Concepts: 03 Logic Gate Characteristics & Buffer Gates | 07 Boolean Algebra Foundations & Duality Principle | 09 XOR Gate Properties, Parity Generator & Error Checking

10 Universal Logic Gates (NAND & NOR Implementation)

What is a Universal Logic Gate?

A logic gate is classified as Universal if any arbitrary Boolean function or digital logic circuit can be completely implemented using only that single type of gate, without requiring any other logic gates {such as separate AND, OR, or NOT gates}.

In digital electronics, both NAND and NOR gates are Universal Gates.

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1. NAND Gate Realizations

The fundamental rule for NAND gate synthesis relies on input tying:

Tying both inputs of a 2-input NAND gate together transforms it into a NOT Gate (Inverter). Proof: $F=\overline{A\cdot A}=\bar{A}$.

NAND as NOT:  A ---+---\ NAND )o---> A'
                   +---/

graph TD
    subgraph 4-NAND Gate XOR Network
        InA[Input A] & InB[Input B] --> NAND1[NAND 1: Output N1 = AB']
        InA & NAND1 --> NAND2[NAND 2: Output N2 = A • N1 ']
        InB & NAND1 --> NAND3[NAND 3: Output N3 = B • N1 ']
        NAND2 & NAND3 --> NAND4[NAND 4: Output F = A ⊕ B]
    end

Implementing 5 Basic Logic Gates Using NAND Gates Only:

1. NOT Gate (Requires 1 NAND Gate)

• Circuit: Connect input signal $A$ to both inputs of a single NAND gate.
• Equation: $F=\overline{A\cdot A}=\bar{\mathbf{A}}$.

2. AND Gate (Requires 2 NAND Gates)

• Circuit:
  1. Pass inputs $A$ and $B$ into NAND Gate 1 $\to$ Output = $\overline{AB}$.
  2. Invert the output using NAND Gate 2 (inputs tied together).
• Equation: $F=\overline{\overline{AB}}=\mathbf{AB}$.

3. OR Gate (Requires 3 NAND Gates)

• Circuit:
  1. Pass input $A$ through NAND Gate 1 (as NOT) $\to \bar{A}$.
  2. Pass input $B$ through NAND Gate 2 (as NOT) $\to \bar{B}$.
  3. Feed $\bar{A}$ and $\bar{B}$ into NAND Gate 3.
• Equation: $F=\overline{\bar{A}\cdot \bar{B}}=\overline{\stackrel{ˉ}{A}}+\overline{\stackrel{ˉ}{B}}=\mathbf{A}+\mathbf{B}$ (by De Morgan’s Law).

4. NOR Gate (Requires 4 NAND Gates)

• Circuit: Take the 3-NAND OR gate output ($A+B$) and pass it through a 4th NAND gate acting as an inverter.
• Equation: $F=\overline{\mathbf{A}+\mathbf{B}}$.

5. XOR Gate (Requires 4 NAND Gates)

• Circuit Network:
  1. NAND 1: Receives inputs $A$ and $B\to \overline{AB}$.
  2. NAND 2: Receives input $A$ and output of NAND 1 $\to \overline{A\cdot \overline{AB}}$.
  3. NAND 3: Receives input $B$ and output of NAND 1 $\to \overline{B\cdot \overline{AB}}$.
  4. NAND 4: Receives outputs of NAND 2 and NAND 3.
• Equation: $F=\overline{\overline{A\cdot \overline{AB}}\cdot \overline{B\cdot \overline{AB}}}=A\bar{B}+\bar{A}B=\mathbf{A}\oplus \mathbf{B}$.

6. XNOR Gate (Requires 5 NAND Gates)

• Circuit: Pass the 4-NAND XOR output ($A\oplus B$) through a 5th NAND gate acting as an inverter.
• Equation: $F=\mathbf{A}\odot \mathbf{B}$.

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2. NOR Gate Realizations

The fundamental rule for NOR gate synthesis relies on input tying:

Tying both inputs of a 2-input NOR gate together transforms it into a NOT Gate (Inverter). Proof: $F=\overline{A+A}=\bar{A}$.

NOR as NOT:   A ---+---\ NOR  )o---> A'
                   +---/

graph TD
    subgraph 5-NOR Gate XOR Network
        InA[Input A] & InB[Input B] --> NOR1[NOR 1: Output N1 = A+B ']
        InA & NOR1 --> NOR2[NOR 2: Output N2 = A + N1 ']
        InB & NOR1 --> NOR3[NOR 3: Output N3 = B + N1 ']
        NOR2 & NOR3 --> NOR4[NOR 4: Output N4 = A ⊙ B XNOR]
        NOR4 --> NOR5[NOR 5 Inverter: Output F = A ⊕ B XOR]
    end

Implementing 5 Basic Logic Gates Using NOR Gates Only:

1. NOT Gate (Requires 1 NOR Gate)

• Circuit: Connect input signal $A$ to both inputs of a single NOR gate.
• Equation: $F=\overline{A+A}=\bar{\mathbf{A}}$.

2. OR Gate (Requires 2 NOR Gates)

• Circuit:
  1. Pass inputs $A$ and $B$ into NOR Gate 1 $\to$ Output = $\overline{A+B}$.
  2. Invert the output using NOR Gate 2 (inputs tied together).
• Equation: $F=\overline{\overline{A+B}}=\mathbf{A}+\mathbf{B}$.

3. AND Gate (Requires 3 NOR Gates)

• Circuit:
  1. Pass input $A$ through NOR Gate 1 (as NOT) $\to \bar{A}$.
  2. Pass input $B$ through NOR Gate 2 (as NOT) $\to \bar{B}$.
  3. Feed $\bar{A}$ and $\bar{B}$ into NOR Gate 3.
• Equation: $F=\overline{\bar{A}+\bar{B}}=\overline{\stackrel{ˉ}{A}}\cdot \overline{\stackrel{ˉ}{B}}=\mathbf{AB}$ (by De Morgan’s Law).

4. XNOR Gate (Requires 4 NOR Gates)

• Circuit Network:
  1. NOR 1: Receives inputs $A$ and $B\to \overline{A+B}$.
  2. NOR 2: Receives input $A$ and output of NOR 1 $\to \overline{A+\overline{A+B}}$.
  3. NOR 3: Receives input $B$ and output of NOR 1 $\to \overline{B+\overline{A+B}}$.
  4. NOR 4: Receives outputs of NOR 2 and NOR 3.
• Equation: $F=\mathbf{A}\odot \mathbf{B}=AB+A^{\prime }{B}^{\prime }$ (The XNOR function).

5. XOR Gate (Requires 5 NOR Gates)

• Circuit: Pass the 4-NOR XNOR output ($A\odot B$) through a 5th NOR gate acting as an inverter.
• Equation: $F=\overline{A\odot B}=\mathbf{A}\oplus \mathbf{B}$.

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3. Summary of Gate Counts for Universal Realizations

Target Logic Gate	Number of NAND Gates Required	Number of NOR Gates Required
NOT	1	1
AND	2	3
OR	3	2
NAND	1 (Native)	4
NOR	4	1 (Native)
XOR	4	5
XNOR	5	4

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Past Year Questions (PYQs)

5-Gate NOR Network Verification PYQ

Question: Show mathematically that the 5-gate NOR network circuit yields an Exclusive-OR (XOR) output.

Proof Solution:

1. Output of NOR 1: $N_1=\overline{A+B}$.
2. Output of NOR 2: $N_2=\overline{A+\overline{A+B}}=\overline{A+A^{\prime }{B}^{\prime }}=A^{\prime }\cdot (A+B)=A^{\prime }B$.
3. Output of NOR 3: $N_3=\overline{B+\overline{A+B}}=\overline{B+A^{\prime }{B}^{\prime }}=B^{\prime }\cdot (A+B)=A{B}^{\prime }$.
4. Output of NOR 4 (XNOR): $N_4=\overline{A^{\prime }B+A{B}^{\prime }}=\overline{A\oplus B}=A\odot B$.
5. Output of NOR 5 (Inverter): $F=\overline{N_4}=\overline{\overline{A\oplus B}}=\mathbf{A}\oplus \mathbf{B}$.
6. Thus, the 5-gate NOR network is proven to yield an XOR gate. $■$