Here is the systematically categorized question bank based on the provided exam papers from 2015 to 2025. The questions have been divided into major topics and subtopics, preserving exact wording, marks, and figure references as requested.
Topic 1: Number Systems and Codes
| Subtopic | Exact Question | Year(s) of Appearance |
|---|---|---|
| Base Conversions | Convert the following numbers from the given base to the bases indicated: (i) Decimal number 249.6 to base-3, base-4, and base-7. (ii) Hexadecimal 2AC5.D to decimal, octal, and binary. (12) | 2015, 2016, 2022 |
| Convert the following numbers from the given base to the bases indicated: i. Decimal number 238.7 to base 3, base 4 and base 7. ii. Hexadecimal 2CA5.D to decimal, octal and binary. (12) | 2017 | |
| Explain the distinction between number system and code with example. Convert the decimal number (605)₁₀ into following forms: (i) BCD code; ii) 5211 code; and iii) Gary code number. (12) | 2018 | |
| Represent the decimal number 8620 (i) in BCD, (ii) in excess-3 code, (iii) in 2,4,2,1 code, and (iv) as a binary number. (08) | 2019 | |
| Do the following conversion problems: i. Convert decimal 27.315 to binary. ii. Calculate the binary equivalent of 2/3out to eight places. Then, convert from binary to decimal. How close is the results to 2/3? iii. Convert the binary result in (b) into hexadecimal. Then, convert the result to decimal. Is the answer same? (12) | 2021 | |
| Convert following numbers from given base to bases indicated. (i) Decimal number 249.6 to base-4 and base-7. (ii) Calculate the binary equivalent of 2/3 out of eight places. Then convert from binary to decimal. How close is the result to 2/3? (iii) Convert the binary result in (ii) into hexadecimal. Then convert the result to decimal. Is the answer same? (12) | 2023 | |
| Convert following numbers from given base to bases indicated. (i) Decimal number 247.8 to base-3, base-7, and base-12. (ii) Hexadecimal 2AC5.D to binary, octal, and decimal. (12) | 2025 | |
| Binary Arithmetic & Complements | Perform the subtraction with the following binary numbers using (i) 2’s complement and (ii) 1’s complement, Check the answer by straight subtraction: (1110110-111)₂ (13) | 2015 |
| A and B are integer variables in a computer program, with A = (25)₁₀ and B = -(46)₁₀. Assuming that the computer uses 8-bit two’s complement arithmetic, show how it would compute A+B, A-B, B-A and -A-B. (13) | 2016, 2017 | |
| Perform the subtraction with following binary number using i) 2’s complement, ii) 1’s complement; iii) Check the answer by straight subtraction 100 -11000. (09) | 2018 | |
| Perform the subtraction with the following binary numbers using (i) 2’s complement and (ii) 1’s complement. Check the answer by straight subtraction. (100 - 110000)₂. (10) | 2019 | |
| A and B are integer variables in a computer program, with A=(x)₁₀ and B=-(y)₁₀. Assuming that the computer uses 8-bit two’s complement arthematics, show how it would compute A+B, A-B, B-A and -A-B. Here X = (Last two digit of your Roll number + 5) Y = (Last two digit of your Roll number + 25) (12) | 2020 | |
| A and B are integer variables in a computer program with A = (25)₁₀ and B = -(48)₁₀. Assuming that the computer uses 8-bit two’s complement arithmetic, show how it would compute A + B, A - B, B - A and -A - B. (13) | 2021 | |
| Multiply the following numbers in the given base without converting to decimal. (i) (135.4)₆ and (43.2)₆, (ii) (367)₈ and (715)₈. (08) | 2024 | |
| A and B are integer variables in a computer program A = (25)₁₀ and B = -(48)₁₀. Assume the computer 8-bit two’s complement arithmetic. Compute A+B, B-A. (08) | 2025 | |
| Digital Codes & Definitions | Define the following terms: (i) Error detection code, (ii) Reflected code, (iii) Self-complementary code, (iv) Decoder, (iv) PLA (10) | 2017 |
| Explain the differences between error detecting codes and error correcting codes (04) | 2018 | |
| Define self-complementary code. “Excess-3 code is a self-complementary code”- justify the statement. (10) | 2021 | |
| What is self-complementary code? “Excess-3 code is a self-complementary code”- justify the statement. (09) | 2023 | |
| What is self-complementary code? “Excess-3 code is a self-complementary code”- justify the statement. (08) | 2025 |
Topic 2: Introduction to Digital Electronics & Logic Families
| Subtopic | Exact Question | Year(s) of Appearance |
|---|---|---|
| Introduction | What is digital electronics? Why the study of digital electronics is necessary for the students of ECE department ? (10) | 2020 |
| Describe the importance of digital electronics. (08) | 2024 | |
| Why digital electronics is important to study for ECE graduates? (07) | 2025 | |
| Logic Families & Characteristics | ”Open collector TTL gates are tied together to form a wired-AND logic”-Justify the statement. (11) | 2015 |
| Define the following terms that relate with the characteristics of digital logic families. (i) Fan-out, (ii) Power distribution, (iii) Propagation delay, (iv) Noise margin. (10) | 2016 | |
| Show that the circuit shown in Fig. 4(b) behaves as an inverter with the following parameters: Rc=1 kΩ, Rb=22 kΩ, Vcc=5 V, hfe=50, H=5 V (High level voltage), L=0.2V (Low level voltage) (Figure Fig. 4(b)) (13) | 2016 | |
| Define the following terms that relate with the characteristics of digital logic families: i) Fan out, ii) Power distribution; iii) Propagation delay; and iv) Noise margin. (08) | 2018 | |
| Describe the operation of the Fig.4(d) and find out the output value of y for all possible combination of inputs A, B and C. (Figure Fig. 4(d)) (09) | 2018 | |
| Define Fan out and Noise margin characteristics of digital logic families and show the circuit of three inputs NAND gate using CMOS transistors. (05) | 2019 | |
| Explain the operation of common bus system using open collector gates. (07) | 2019 | |
| Show that the circuit in figure 4(b) behaves as an inverter with the following parameters: Rc = 1 KΩ, Rb = 22 KΩ, Vcc = 5V, hfe = 50, H = 5V (high level volatge), L = 0.2V (low level voltage). (Figure Fig. 4(b)) (13) | 2019 | |
| Define the following terms that relate with the characteristics of digital logic families: (i) Fan out (ii) Propagation delay (iii) Power distribution (iv) Noise margin. (10) | 2021 | |
| Describe the most important characteristics that are considered to evaluate the basic gate of digital logic families. (07) | 2021 | |
| Show that the output transistor of the DTL gate of Fig. 4(d) goes into saturation when all inputs are high. Assume that hFE = 20. (Figure Fig. 4(d)) (10) | 2021 | |
| Draw and explain the Transistor Base and Transistor Collector characteristics for an npn silicon transistor. (09) | 2022 | |
| Show that the output transistor of the DLT gate of the Fig. 4(b) goes into saturation when all inputs are high. Assume that hFE = 20. (Figure Fig. 4(b)) (10) | 2022 | |
| Define the following terms that relate with the characteristics of digital logic gates: (i) Fan out, (ii) Propagation delay, (iii) Noise margin. (06) | 2023 | |
| Draw the circuit and explain the operation of TTL logic AND gate by using the truth table. (09) | 2023 | |
| Define: (i) Fan-out, (ii) Propagation delay, (iii) Power dissipation, and (iv) Noise Margin. (08) | 2024 | |
| Define: (i) Fan-out, (ii) Noise Margin, (iii) Propagation delay, and (iv) Current Sourcing. (08) | 2025 | |
| Explain the working principle with necessary diagram of a TTL NAND gate. (08) | 2025 |
Topic 3: Boolean Algebra & Logic Gates
| Subtopic | Exact Question | Year(s) of Appearance |
|---|---|---|
| Postulates, Theorems & Definitions | Define the following terms: (i) Duality principle, (ii) Canonical form, (iii) Standard form, (iv) Positive and Negative logic system, (v) IC logic families. (10) | 2015 |
| Define the following terms: (i) Duality principle, (ii) canonical form, (iii) standard form, (iv) positive and negative logic system, (v) IC logic families. (10) | 2016 | |
| Define the following terms: (i) Duality principle (ii) Standard form (08) | 2019 | |
| Define the following terms: (i) Duality principle (ii) Standard form. (06) | 2022 | |
| What is duality principle? Find the complement of the following Boolean function and reduce this complement function to a minimum number of literals: F = [(AB)’ A] [(AB)‘B] (10) | 2018 | |
| Define universal gate. Distinguish between canonical form and standard form of a Boolean function. (10) | 2021, 2022 | |
| What is meant by canonical and standard form? Express the Boolean function F = xy + xz in a product of maxterm from. (09) | 2024 | |
| Show that (i) The Dual of the exclusive-OR is equal to its complement (ii) a Positive-logic AND gate is a Negative-logic OR gate and Vice-versa. (12) | 2015 | |
| Show that (i) the dual of the exclusive OR is equal to its compliment and (ii) a positive logic AND a negative logic OR gate and vice-versa (10) | 2018 | |
| Show that a positive-logic AND gate is a negative-logic OR gate and vice-versa. (11) | 2019 | |
| Show that a positive logic AND gate is a negative logic OR gate and vice-versa. (10) | 2023 | |
| Show that a positive logic AND gate is a negative logic OR gate and vice-versa. (07) | 2025 | |
| Show that the circuit in Fig. 3(a) is an Exclusive-OR. (Figure Fig. 3(a)) (11) | 2015 | |
| Show that the circuit in Fig. 3(b) is an exclusive - OR. (Figure Fig. 3(b)) (08) | 2021 | |
| Boolean Function Simplification | Express the following function in a Sum of Minterms and a Product of Maxterms. F(A,B,C,D) = (A+B’+C)(A+B’)(A+C’+D’)(A’+B+C+D’)(B+C’+D’) (12) | 2015 |
| Given the function f(A,B,C) = (A+B+C’)(A+B’+C’)(A’+B+C’)(A’+B’+C’), let construct the truth table and express the function in both maxterm and minterm forms. (12) | 2016 | |
| Express the following functions in a sum of Minterms and a product of Maxterms: i. F(A,B,C) = (A’ + B)(B’ + C) ii. F(x,y,z) = (xy + z)(y + xz) (12) | 2017 | |
| Express the following functions in a sum of Minterms and a product of Maxterms. i. F(A,B,C) = (A’ + B)(B’ + C) ii. F(x,y,z) = (xy + z)(y + zx) (10) | 2021 | |
| Express the following function in a sum of minterms and a product of maxterms. F(w,x,y,z) = y’z + wxy’ + wxz’ + w’x’z (09) | 2019 | |
| Convert each of the following expressions into Sum of Products and Product of Sums: (i) (AB + C) (B + C’D) (ii) x’ + x(x + y’) (y + z’) (10) | 2022 | |
| Obtain the simplified expression in (i) Sum of products and (ii) Product of sums. (A’+ B’+ D’)(A + B’+ C’)(A’+ B + D’)(B + C’+ D’) (12) | 2019 | |
| Minimize the following function in both SOP and POS forms using K-maps. f(A,B,C,D) = ∑m(1,3,4,7,11) + d(5,12,13,14,15) (13) | 2016 | |
| With the use of K-map, find the simplest sum- of -products from of the function F = fg. Where f = abc’ + c’d + a’cd’ + b’cd’ and g = (a + b + c + d’)(b’ + c’ + d)(a’ + c + d’) (10) | 2018 | |
| With the use of maps, find the simplest Sum-of-Products form of the function F = fg, where f = abc’ + c’d + a’cd’ + b’cd’ and g = (a + b + c’ + d’) (b’ + c’ + d) (a’ + c + d’). (07) | 2022 | |
| Simplify the following Boolean expressions, using four-variable maps: (i) A’B’C’D’ + A’CD’ + AB’D’ + ABCD + A’BD (ii) F(w,x,y,z) = ∑(0,1,4,5,6,7,8,9) (10) | 2022 | |
| Simplify the following Boolean expression using four variables maps: (i) A’B’C’D’ + A’CD’ + AB’D’ + ABCD + A’BD (ii) F(w,x,y,z) = ∑(0,1,4,5,6,7,8,9). (08) | 2023 | |
| Give three possible ways to express the following Boolean function with eight or fewer literals: F = B’C’D’ + AB’CD’ + BC’D + A’BCD (09) | 2022 | |
| Define and explain prime implicants. (05) | 2018 | |
| Determine the prime-implicants of the following function by using Tabular method: F(w,x,y,z) = ∑(1,4,6,7,8,9,10,11,15) (14) | 2023 | |
| Determine the prime-implicants of the following function by using Tabular method: F(w,x,y,z) = ∑(1,4,6,7,8,9,10,11,15) (10) | 2025 | |
| Simplify the Boolean function by means of the tabulation method. F(A,B,C,D,E,F) = ∑(6,9,13,18,19,25,27,29,41,45,57,61) (10) | 2024 | |
| The following Boolean expression: BE + B’DE’ is a simplified version of the expression? A’BE + BCDE + BC’D’E + A’B’DE’ + B’C’DE’. Are there any don’t care conditions? If so, what are they? (11) | 2017 | |
| The following Boolean expression; BE + B’DE’ is a simplified version of the expression: A’BE + BCDE + BC’D’E + A’B’DE’ + B’C’DE’, are there any don’t care conditions? If so, what are they? (10) | 2020 | |
| Show that A ⊕ B ⊕ C ⊕ D = ∑(0,3,5,6,9,10,12,15) (10) | 2017 | |
| Logic Circuit Simplification & Implementation | Implement the following function using the don’t-care conditions. Assume that both the normal and complement inputs are available. F = A’B’C’ + AB’D + A’B’CD’, d = ABC + AB’D’ with no more than Two NOR gates. (11) | 2015 |
| Implement the following Boolean function F together with the don’t care conditions d, using no more than two NOR gates. F(A,B,C,D) = ∑(2,4,6,10,12) d(A,B,C,D) = ∑(0,8,9,13) Assume that both the normal and complement inputs are available. (08) | 2021 | |
| Simplify the following functions and implement them with two-level NOR gate circuits: i. F(w,x,y,z) = ∑(1,2,13,14) ii. F(x,y,z) = [(x + y)(x’ + z)]’ (07) | 2021 | |
| Implement the following function with NOR gates: F = x’yz’ + xy’z. (08) | 2024 | |
| Find a simplified switching expression and logic network for the logic circuit as shown in Fig. 2(b). (Figure Fig. 2(b)) (12) | 2016 | |
| Simplify the following logic circuit as shown in Fig. 2(c) and construct the simplified circuit using only NAND gates. (Figure Fig. 2(c)) (10) | 2018 | |
| Simplify the following logic circuit as shown in figure 2(b). (Figure Fig. 2(b)) (12) | 2019 | |
| Determine the Boolean function for the output F of the circuit shown in Fig. 2c. (Figure of Q. 2(c)) (10) | 2020 | |
| Simplify the logic circuit shown in Fig. 2(c): (Figure Fig. 2(c)) (08) | 2022 | |
| Represent the logic circuit in Fig. 2(c) with only a single logic gate. (Figure Fig. 2(c)) (08) | 2023 | |
| Express the following switching circuit shown in figure 1(b) in a binary logic notation. (Figure 1(b)) (07) | 2024 | |
| Express the following switching circuit shown in Figure 1.(c) in a binary logic notion (Light in ‘ON’ condition). (Figure of Q. 1(c)) (08) | 2025 |
Topic 4: Combinational Logic Circuits
| Subtopic | Exact Question | Year(s) of Appearance |
|---|---|---|
| Adders & Subtractors | Implement the Four Boolean functions listed using three Half-Adder circuits. D = A ⊕ B ⊕ C, E = A’BC + AB’C, F = ABC’ + (A’+B’)C, G = ABC (12) | 2015 |
| Implement the four Boolean functions listed using three half-adder circuits. D = A ⊕ B ⊕ C, E = A’BC + AB’C, F = ABC’ + (A’+B’)C, G = ABC (12) | 2019 | |
| Implement the four Boolean functions listed below using three half adder circuits: D = A ⊕ B ⊕ C, E = A’BC + AB’C, F = ABC’ + (A’+B’)C, G = ABC (10) | 2018 | |
| Show that the output carry in a full-adder circuit can be expressed as Cᵢ₊₁ = Gᵢ + PᵢCᵢ = Gᵢ’Pᵢ’ + Gᵢ’Cᵢ’ for the full adder circuit shown in Fig. 3(c). (Figure Fig. 3(c)) (10) | 2018 | |
| Implement a full-adder circuit with a decoder and two OR gates. (11) | 2019 | |
| Show that a full adder can be converted full subtractor with the addition of one inverter gate. (10) | 2020 | |
| Implement a full-adder with two 4 × 1 multiplexers. (07) | 2021 | |
| Code Converters & Multipliers | Design a combinational circuit that converts a decimal digit from the 2,4,2,1 code to the 8,4,-2,-1 code. (11) | 2017 |
| Design a combinational circuit that converts a decimal digit from the 2, 4, 2, 1 code to 8, 4, -2, -1 code. (12) | 2019 | |
| Design a combinational circuit that converts a decimal digit from the 2, 4, 2, 1 code to the 8, 4, -2, -1 code. (08) | 2020 | |
| Design a combinational circuit that converts a decimal digit from the 2, 4, 2, 1 code to 8, 4,-2,-1 code. (10) | 2023 | |
| Design a combinational circuit that converts a decimal digit from the 2, 4, 2, 1 code to 8, 4,-2,-1 code. (13) | 2024 | |
| Design a combinational circuit that converts a decimal digit from the 2, 4, 2, 1 code to 8, 4,-2,-1 code. (09) | 2025 | |
| Design a combination circuit that accepts a four-bit BCD number and generates output binary number same as the excess-3 code of corresponding BCD number. (10) | 2018 | |
| Design a combinational circuit that converts a four bit reflected code number to a four bit binary number. Use X-OR gates. (10) | 2024 | |
| The Fig. 4(d) represents a multiplier circuit that takes two-bit binary numbers x₁x₀ and y₁y₀ and produces an output binary number z₃z₂z₁z₀ that is equal to the arithmetic product of the two input numbers. Design the logic circuit for the multiplier. (Figure Fig. 4(d)) (10) | 2022 | |
| Decoders, Multiplexers & Demultiplexers | Design a 16-to-1 multiplexer by using 4-to-1 multiplexers that can be used for a tree type network. (12) | 2016 |
| Design a 16-to-1 multiplexer by using 4-to-1 multiplexers that can be used for a tree type network. (11) | 2017 | |
| Implement the following function with a multiplexer. f(A,B,C,D) = ∑(0,1,3,4,8,9,15) (10) | 2016 | |
| Define multiplexer and demultiplexer. Implement the following function with a multiplexer. F(A,B,C,D) = ∑(0,2,3,4,8,10,14) (10) | 2019 | |
| Implement the following function with a multiplexer. F(A,B,C,D) = ∑(0, 2, 3, 4, 8, 10, 14) (10) | 2023 | |
| Implement the following function with a 8×1 multiplexer: F(A,B,C,D) = ∑(0,1,3,4,8,9,15) (10) | 2024 | |
| Design a 4 -to- 1line multiplexer using NAND gates. (10) | 2018 | |
| Construct a 4-to-16 line decoder with five 2-to-4 line decoders with enable. (10) | 2021 | |
| What is a Decoder? Implement the following function using Decoder, F(A,B,C,D) = ∑(0,1,3,4,8,9,10,11) (08) | 2018 | |
| A combinational circuit is defined by the following three equations: F₁ = x’y’ + xyz’, F₂ = x’ + y, F₃ = xy + x’y’. Design the circuit with a decoder and external gates. (12) | 2016, 2017 | |
| A combinational circuit is defined by the following three functions; F₁ = x’y’ + xyz’ F₂ = x’ + y, F₃ = xy + x’y’ Design the circuit with a decoder and external gates. (10) | 2020 | |
| Implement the following Boolean function with a 4 × 1 multiplexer and external gates. F(A,B,C,D) = ∑(1,3,4,11,12,13,14,15). (10) | 2022 | |
| Implement a 1×16 demultiplexer using only 2-to-4 decoders with enable inputs and no other logic gates. Clearly label all inputs, pins, and outputs of your circuits. (11) | 2023 | |
| Construct a 5×32 decoder with four 3×8 decoders/demultiplexers and 2×4 decoder. Use a block diagram construction. (08) | 2024 | |
| Construct a 5×32 decoder with four 3×8 decoder/demultiplexers and 2×4 decoder. Use a block diagram construction. (09) | 2025 | |
| ROM, PLA & Parity Checkers | Design a combinational circuit using a ROM. The circuit accepts a 3-bit number and generates an output binary number equal to the square of the input number. (12) | 2015, 2020 |
| Design a combinational circuit using a ROM. The circuit accepts 3-bit number and generates an output binary number equal to the square of the input number. (13) | 2017 | |
| Design a combinational circuit using a ROM. The circuit accepts 3-bit number and generates an output binary number equal to the square of the input number. (08) | 2021 | |
| Design a combinational circuit using a ROM. The circuit accepts a 3-bit number and generates an output binary number equal to the square of the input number. (10) | 2025 | |
| Draw the block diagram of PLA. (05) | 2018 | |
| Distinguish the operation of ROM and PLA. (06) | 2024, 2025 | |
| A combinational circuit is defined by the functions: F₁(A,B,C) = ∑(3,5,6,7), F₂(A,B,C) = ∑(0,2,4,7). Implement the circuit with PLA having three inputs, four product terms and two outputs. (12) | 2015 | |
| A combinational circuit is defined by the functions: F₁(A,B,C) = ∑(3, 5, 6, 7) and F₂(A,B,C) = ∑(0, 2, 4, 7) Implement the circuit with a PLA having three inputs, four product terms, and two outputs. (10) | 2023 | |
| A combinational circuit is defined by the functions: F₁(A,B,C) = ∑(3, 5, 6, 7) and F₂(A,B,C) = ∑(0, 2, 4, 7) Implement the circuit with a PLA having three inputs, four product terms, and two outputs. (11) | 2024 | |
| A combination circuit is defined by the following functions: F₁(A, B, C) = ∑(3, 5, 6, 7) & F₂(A, B, C) = ∑(0, 2, 4, 7). Implement the circuit with a PLA having three inputs, four product terms, and two outputs. (11) | 2025 | |
| Design a combinational circuit to check for even parity of four bits. A logic-1 output is required when the four bits do not constitute an even parity. (12) | 2015 | |
| Design a combinational circuit to check for even parity of four bits. A logic-1 output is required when the four bits do not constitute an even parity. (08) | 2020 | |
| Design a combinational circuit to check for even parity of four bits. A logic 1 output is required when the four bits do not constitute an even parity. (09) | 2023 | |
| Design a combinational circuit to check for even parity of 4 bits. A logic 1 output is required when the 4 bits do not constitute an even parity. (12) | 2024 | |
| Derive the circuits for a three-bit parity generator and four-bit parity checker using an odd parity bit. (08) | 2022 | |
| Design a circuit for a 3-bit parity generator and 4-bit parity checker using odd parity bit. (10) | 2025 | |
| John and Jane Doe have two children, Joe and Sue. When eating out they will go to a restaurant that serves only vegetables or one that serves only chicken. Before going out, the family votes to decide on the restaurant. The majority wins, except Mom and Dad agree, and in that case they win. Any other tie votes produce a trip to the chicken restaurant. We wish to design a logic circuit that will automatically select the restaurant when everyone votes. (11) | 2016 | |
| For the following Fig 3(a), where a analog-to-digital converter is monitoring the dc voltage of a 12V storage battery on an orbiting spaceship. The converters output is a four-bit binary number, ABCD, corresponding to the battery voltage in steps of 1V, with A as the MSB. The converter’s binary outputs are fed to a logic circuit that is to produce a HIGH output as long as the binary value is greater than 0110₂ = 6₁₀; that is, the battery voltage is greater than 6V. Design this logic circuit. (Figure Fig. 3(a)) (13) | 2017 | |
| Gas fired stream boiler is frequently used in power stations. Four sensors are available, one sensor monitors the water temperature, one monitors pressure of the boiler, one monitors the chimney temperature and one follows the flame state of burner. An alarm signal should be generated whenever burner flame is ignited and either chimney temperature or water temperature or boiler pressure is high. Design the logic circuit for the boiler. (10) | 2021 | |
| A 4-bit binary number appear at the inputs of a combinational network. One of the output z₁ indicates if the multi bit input is divisible by 2 without any remainder and the other output z₂ indicates if the multi bit input is divisible by 3 without any remainder. (08) | 2022 | |
| Design a circuit that compares two 4-bit numbers, A and B, to check if they are equal. The circuit has one output x, so that x = 1 if A = B, and x = 0 if A≠B. (14) | 2023 | |
| Design a circuit that compares two 4-bit numbers, A and B, to check if they are equal. The circuit has one output x, so that x = 1 if A = B, and x = 0 if A≠B. (12) | 2024 | |
| Design a circuit that compares two 4-bit numbers, A and B, to check if they are equal. The circuit has one output x, so that x = 1 if A = B, and x = 0 if A≠B. (09) | 2025 |
Topic 5: Sequential Logic Circuits
| Subtopic | Exact Question | Year(s) of Appearance |
|---|---|---|
| Latches & Flip-Flops | Write down the excitation table of RS, D, JK and T flip-flop. (10) | 2015 |
| Write down the characteristics table and excitation table of RS, JK, D and T flip-flop. (10) | 2017, 2018, 2020, 2021 | |
| Draw the diagram of RS, JK, D and T flip-flop. From these diagram write their characteristics tables and derive characteristics equations. (12) | 2016 | |
| Draw the diagram of RS, JK, D, and T flip-flop. Also write their characteristics table and excitation table. (12) | 2019 | |
| Write down the characteristics table and execution table of RS, JK, D, and T Flip-flop. (10) | 2022 | |
| What is flip-flop? Why flip-flop is called one-bit memory cell? (10) | 2018 | |
| Why flip-flop is called one bit memory element? Distinguish combinational circuit and sequential circuit. (6+6) | 2023 | |
| Why flip-flop is called one bit memory element? Distinguish combinational circuit and sequential circuit. (10) | 2024 | |
| Why flip-flop is called one bit memory element? Distinguish combinational circuit and sequential circuit. (5+5) | 2025 | |
| Draw the logic diagram of a clocked master-slave JK flip-flop. (10) | 2015 | |
| Draw the diagram of clocked master-slave JK flip-flop using NAND gates. (08) | 2019 | |
| Show the operation of the D-type edge-triggered flip-flop with necessary diagram. (10) | 2015 | |
| Show the operation of the D-type edge-triggered flip-flop with necessary diagram. (08) | 2016 | |
| Show the operation of the D-type edge triggered flip-flop with necessary diagram. (10) | 2017 | |
| Show the operation of D-type edge-triggered flip-flop with necessary diagrams. (10) | 2019 | |
| Show the operation of D-type edge-triggered flip-flop with necessary diagrams. (12) | 2022 | |
| Why race around condition occurs in JK flip-flop? How this problem can be overcome? (10) | 2017 | |
| Why race around condition occurs in JK flip-flops? Give one solution of this problem. (10) | 2020 | |
| Why race around condition occurs in JK flip-flop? How can this problem be resolved? (10) | 2021 | |
| Convert an S-R flip-flop to a J-K flip flop. (10) | 2017 | |
| Convert a SR flip-flop to a JK flip-flop. (10) | 2018 | |
| Convert a J-K flip-flop to a S-R flip-flop. (12) | 2024 | |
| ”JK flip-flop is the refinement of RS flip-flop”- justify the statement. (11) | 2023 | |
| ”JK flip-flop is the refinement of RS flip-flop”- justify the statement. (09) | 2025 | |
| For a JK flip-flop, obtain the flip-flop (i) Characteristic table, (ii) Characteristic equation, (iii) Excitation table and (iv) Show that tying the two external inputs together forms a D flip-flop. (13) | 2024 | |
| State Machines (Analysis & Design) | What is sequential circuit? Draw the block diagram of a sequential circuit. (05) | 2017, 2019 |
| Mention the procedures to design of sequential circuits. (10) | 2024 | |
| Define state table, state diagram and state equation. (08) | 2015, 2016 | |
| Define: State table, State diagram, State equation and Register. (10) | 2022 | |
| Define State table, State diagram and State equation. An example of clocked sequential circuit is shown in figure 7(b). Obtain the state table of the sequential circuit. (Figure Fig. 7(b)) (10) | 2021 | |
| What is sequential circuit? Write down the state table and draw the state diagram of the following sequential circuit. (Figure Fig. 5(a)) (10) | 2016 | |
| Write down the state table and draw the state diagram of the following sequential circuit. (Figure Fig. 6(a)/6(b)/5(a)) (12) | 2015, 2019 | |
| Write down the state table and draw the state diagram of the following sequential circuit. (Figure of Q. 5(a)) (10) | 2020 | |
| Analyze the following circuit shown in Figure 6(b) and write down the state table and state diagram. (Figure Fig. 6(b)) (12) | 2022 | |
| A sequential circuit has one input and one output. The state diagram is shown in Figure 6(a). Design the sequential circuit with T flip-flops. (Figure Fig. 6(a)) (12) | 2017 | |
| The specification of a sequential circuit is given in the state diagram shown in figure 5(c). From this, design a sequential circuit that will have minimum number of states. (Figure Fig. 5(c)) (15) | 2021 | |
| Design a sequential circuit whose state equations are given below: A₁(t+1) = ∑(4,6), A₂(t+1) = ∑(1,2,5,6), y(A₁,A₂,x) = ∑(3,7) (12) | 2021 | |
| Design a sequential circuit whose state equations are given below: A₁(t+1) = ∑(4, 6), A₂(t+1) = ∑(1, 2, 5, 6), y(A₁, A₂, x) = ∑(3, 7). (12) | 2023 | |
| Design a sequential circuit described by the following state equations using JK flip-flop. A(t+1) = xAB + yA’C + xy, B(t+1) = xAC + yB’C’, C(t+1) = x’B + yA’B’ (12) | 2024 | |
| Design a sequential circuit described by the following state equations using J-K flip-flop. A(t+1) = xAB + yA’C + xy, B(t+1) = xAC + yB’C’, C(t+1) = x’B + yA’B’ (12) | 2025 | |
| Design a serial adder using a sequential logic procedure. (10) | 2019 | |
| State Reduction | Write down the state reduction algorithm. (05) | 2015, 2016, 2018 |
| Reduce the number of states shown in the following sate table and tabulate the reduced sate table. Starting from state a of the reduced state table, find the output sequence generated with an input sequence of 01110010011. (15) | 2016 | |
| Reduce the number of state in the following state table and tabulate the reduced state table: (10) | 2018 | |
| Design a sequential circuit that will represent the reduced form of the following state table. (13) | 2022 | |
| Design a sequential circuit that represents the reduced form of the following state table. (12) | 2023 | |
| Design a sequential circuit that represents the reduced form of the following state table. (10) | 2025 | |
| Design a sequential circuit that represents the minimum number of states for the following state table. For an input sequence 01110010011, compare the output sequences with the given table and the resultant table. (13) | 2024 |
Topic 6: Registers & Counters
| Subtopic | Exact Question | Year(s) of Appearance |
|---|---|---|
| Registers | What is register? Design a 4-bit register with parallel load using D flip-flops and explain its operation. (15) | 2015 |
| What is register? Design a 4-bit register with parallel load using D flip-flops and explain its operation. (12) | 2017 | |
| What is shift register? Draw the diagram of a 4-bit register with parallel load using D flip-flop. (10) | 2016 | |
| What is register? Draw the diagram of a 4-bit register with parallel load using D-flip-flops and external gates. (10) | 2021 | |
| What is register? Draw the diagram of a 4-bit register with parallel load using D flip-flop. (3+7) | 2023, 2025 | |
| What the difference between serial and parallel transfer? What type of register is used in each case? (07) | 2018 | |
| The state of a 12-bit register is 100010010111. What is its content if it represents: (i) Three decimal digits in BCD? (ii) Three decimal digits in the excess-3 code? (iii) Three decimal digits in the 8-4-2-1 code? (iv) A binary number? (12) | 2022 | |
| The content of the shift register A is 1101 in Fig. 7(b), what will be the content of register A and B after 6 clock pulses considering register B is initially cleared. Show the result for each clock pulse. (Figure Fig. 7(b)) (10) | 2016 | |
| The content of the shift register A and B is 1011 and 1101 as shown in figure 7(b). What will be the content of each register after 6 clock pulses? Show the result for each clock pulse. (Figure Fig. 7(b)) (12) | 2019 | |
| The content of the shift register A and B is 1011 and 1101 as shown in Fig. 7(b). What will be the content of each registers upon the application of 6 clock pulses serially? (Figure Fig. 7(b)) (12) | 2022 | |
| The content of a 4-bit shift register is initially 1101. The register is shifted six times to right with the serial input being 101101. What is the content of the register after each shift? (10) | 2017, 2021 | |
| The content of a 4-bit shift register is initially 1101. The register is shifted six times to right with the serial input being 101101. Show the content of the register after each shift? (12) | 2018 | |
| The content of a 4-bit shift register is initially 1011. The register is shifted seven times to right with serial input 1011011. What will be the content of the register after each shift? (12) | 2023 | |
| The content of a 4-bit shift register is initially 1011. The register is shifted seven times to right with serial input 1011011. What will be the content of the register after each shift? (10) | 2025 | |
| The content of a 5-bit shift register is initially 10110. The register is shifted six times to right with serial input 101100. What will be the content of the register after each shift? (10) | 2020, 2024 | |
| Counters | Design a synchronous counter that will count 15-10-9-8-7-6 and repeat by using JK flip-flops. (13) | 2015 |
| Design a synchronous counter that will count 15-10-9-8-7-6 and repeat by using JK flip-flops. (10) | 2020 | |
| Design a synchronous counter that will count 15-10-9-7-8-6 and repeat using JK flip-flops. (15) | 2016 | |
| Design a synchronous counter that will count 15-10-9-7-8-6 and repeat using JK flip-flops. (13) | 2022 | |
| Design a synchronous counter that will count 15-10-9-7-8-6 and repeat using T flip-flop. (13) | 2023 | |
| Design a synchronous counter that will count 15-10-9-8-6-7 and repeat using T flip-flop. (13) | 2025 | |
| Design a counter that will follow the sequence 15-11-9-8-4-6-1 and repeat using T flip-flop. (12) | 2024 | |
| Construct a Johnson counter with Ten timing signals. (10) | 2015 | |
| Construct a Johnson counter with 10 timing signals. (10) | 2018, 2019 | |
| Construct a John Counter with 10 timing signals. (09) | 2025 | |
| Design a counter that counts the decimal digits according to 842̅1̅ code using T flip-flop. (12) | 2016 | |
| Design a counter that counts the decimal digits according to 842̅1̅ code using T flip-flop. (11) | 2017 | |
| Design a counter that counts the decimal digits according to 842̅1̅ code using T flip-flop. (10) | 2020 | |
| Design a counter that counts the decimal digits according to Excess- 3 code using T flip-flop. (13) | 2019 | |
| Design a counter that counts the decimal digits according to Excess-3 code using T flip-flop. (13) | 2022 | |
| Design a decade counter to count excess-3 code sequence using minimum number of J-K flip-flops. (13) | 2024 | |
| Design a decade counter to count excess-3 code sequence using minimum number of J-K flip-flop. (10) | 2025 | |
| Design a BCD counter with JK flip-flops. (10) | 2019 | |
| Design a mod-6 counter using a counter with parallel load. (12) | 2017 | |
| Design a Mod-6 counter using a counter with parallel load. (13) | 2021 | |
| What is Ripple counter. Draw the diagram of a 4-bit synchronous binary up-down counter. (10) | 2018 | |
| What is ripple counter? Draw the diagram of a 4-bit synchronous binary up-down counter. (10) | 2022, 2023 | |
| What is ripple counter? Draw the diagram of a 4-bit synchronous binary up-down counter. (09) | 2025 | |
| Draw the diagram of a 4-bit synchronous binary up-down counter. (05) | 2021 | |
| A flip-flop has a 20-ns delay from the time, its CP input goes from 1 to 0 to the time the input is complemented. What is the maximum delay in a 10-bit binary ripple counter that use these flip-flops? What is the maximum frequency that the counter can operate at reliably? (13) | 2018 |
Topic 7: Data Converters (A/D & D/A) & Memory
| Subtopic | Exact Question | Year(s) of Appearance |
|---|---|---|
| Memory Elements | What is memory element? Show the information transfer process in a magnetic core memory during write operation. (08) | 2015 |
| What is memory element? Show the information transfer process in a magnetic core memory during write operation? (08) | 2018 | |
| What is memory element? Show the information transfer process in a magnetic core memory during write operation. (10) | 2020 | |
| Show the information transfer process in a magnetic core memory during write operation. (10) | 2016 | |
| Define memory element. Show the information transfer process in a magnetic core memory during write operation. (10) | 2019 | |
| What is memory element? Show the information transfer process in a magnetic core memory during read and write operation. (10) | 2022 | |
| Define memory element. Show the information transfer process in a magnetic core memory during write and read operation. (3+7) | 2023 | |
| Draw the diagram of information transfer system in a magnetic core memory during read and write operation. Also explain the operating principle. (12) | 2021 | |
| Write is down the basic properties of the components that forms the binary cells of registers in memory unit? (06) | 2016 | |
| Write short notes on EPROM and E²PROM. (07) | 2015 | |
| Write short notes on EPROM and E²PROM. (08) | 2016, 2017, 2019 | |
| Write short note on EPROM and E²P ROM. (08) | 2018 | |
| Write short notes on EPROM and E²PROM. (10) | 2021 | |
| Write short notes on EPROM. (05) | 2022 | |
| Write short notes on EPROM and E²PROM. (06) | 2023, 2024, 2025 | |
| A/D and D/A Converters | Show that in a Dual slope A/D converter the output of the converter is proportional to the analog input voltage. (12) | 2015 |
| Show that in a Dual slope A/D converter, the output of the converter is proportional to the analog input voltage. (11) | 2016 | |
| Show that in a dual slop A/D converter, the output of the counter is proportional to the analog voltage. (12) | 2017 | |
| Show that in a dual slope A/D converter, the output of the converter is proportional to the analog input voltage. (10) | 2018 | |
| Show that in Dual slope A/D converter, the output of the converter is proportional to the analog input voltage. (13) | 2019 | |
| Show that the output of the counter of a dual slope A/D converter is proportional to the analog voltage. (10) | 2020 | |
| Show that in a dual slop A/D Converter, the output of the converter is proportional to the analog input voltage. (08) | 2021 | |
| Design a dual slop A/D converter where the output of the converter will be proportional to the analog input voltage. (13) | 2022 | |
| Show that in a dual slope A/D converter, the output of the converter is proportional to analog output voltage. (13) | 2023 | |
| For an A/D converter that is often used in digital voltmeter, prove that output of the counter is proportional to the analog input voltage. (13) | 2024 | |
| Define (i) Resolution, (ii) Accuracy, (iii) Settling time. (06) | 2024 | |
| Define (i) Resolution, (ii) Settling time, and (iii) Accuracy. (06) | 2025 | |
| Compare weight-resister and R-2R ladder D/A converter. (09) | 2017 | |
| Write down the differences between R-2R ladder and weighted register D/A converter. (07) | 2018, 2019, 2022, 2023 | |
| Compare weighted-register and R-2R ladder D/A converter. (10) | 2020 | |
| Compare weighted register and R-2R ladder D/A. (08) | 2025 | |
| For an R-2R ladder D/A converter, prove that analog output voltage is proportional to the digital input. (10) | 2024 | |
| For an R-2R ladder D/A converter, prove that analog output voltage is proportional to the digital input. (09) | 2025 | |
| Show the successive approximation A/D conversion process with necessary diagram. (10) | 2015, 2018 | |
| Design a successive approximate in A/D converter that can find an unknown weight in the range 0 to 1 kg using a balance and a set of weights of 1/2, 1/4 and 1/8 kg. (15) | 2021 | |
| Design a successive approximation A/D converter that can find an unknown weight in the range 0 to 1 kg using a balance and a set of weights of ½, ¼, and ⅛ kg. (12) | 2023 | |
| Design a successive approximation A/D converter that can find an unknown weight in the range 0 to 1 kg using a balance and a set of weights of 1/2, 1/4, and 1/8 kg. (09) | 2025 | |
| Design a 2-decade BCD D/A converter. (10) | 2015 |