04 Master Glossary & Formula Sheet for Instructor 2 (Foysal Sir)
Overview: Complete exam-ready master reference sheet containing all core definitions (with PYQ appearance years) and mathematical formulas for Instructor 2 (Foysal Sir) covering Sequential Logic, Flip-Flops, Registers, Counters, Multivibrators, Memory Systems, and Data Converters (DAC/ADC)**.
1. Master Glossary of Definitions [PYQ: 20152025]
1.1 Sequential Logic & Flip-Flops
| Term | Exam-Ready Definition | Year of Appearance |
|---|---|---|
| Sequential Circuit | A digital circuit whose current output depends on both present inputs and historical execution states stored in memory elements. | 2023, 2024, 2025 |
| Flip-Flop | A bistable multivibrator capable of storing exactly one bit of binary data (0 or 1). | 2018, 2023, 2024, 2025 |
| State Table | A tabular mapping showing Present State (Qn), External Inputs (X), Next State (Qn+1), and Present Outputs (Y). | 2015, 2016, 2021, 2022 |
| State Diagram | A directed graph where nodes represent discrete states and directed arrows denote transitions labeled as Input / Output. | 2015, 2016, 2021, 2022 |
| State Equation | An algebraic Boolean expression defining the next state Qn+1 as a function of Qn and inputs. | 2015, 2016, 2021 |
| Race-Around Condition | In a level-triggered JK flip-flop, continuous output toggling during CLK=1 when pulse width exceeds gate delay (tp > tpd). | 2017, 2020, 2021 |
| Equivalent States | Two states that produce identical output sequences and transition to identical or equivalent next states for every input sequence. | 2015, 2016, 2018 |
1.2 Registers, Counters & Multivibrators
| Term | Exam-Ready Definition | Year of Appearance |
|---|---|---|
| Register | An array of N flip-flops clocked simultaneously to store an N-bit binary word. | 2015, 2016, 2017, 2021, 2023, 2025 |
| Ripple Counter | An asynchronous counter where only the LSB flip-flop is clocked externally, and subsequent flip-flops are clocked by preceding outputs. | 2018, 2022, 2023, 2025 |
| Johnson Counter | An N-bit shift register with inverted feedback to D0, generating 2N timing signals. | 2015, 2018, 2019, 2025 |
| Astable Multivibrator | A free-running oscillator with zero stable states and two quasi-stable states, producing continuous square waves. | 2015, 2017, 2018, 2020, 2024 |
| Monostable Multivibrator | A pulse-stretching circuit with 1 stable state and 1 quasi-stable state, producing a single pulse of duration tW upon triggering. | 2017, 2023 |
1.3 Memory Systems & Data Converters
| Term | Exam-Ready Definition | Year of Appearance |
|---|---|---|
| SRAM vs. DRAM | SRAM uses 6T flip-flop latches (no refresh required); DRAM uses 1T1C storage capacitors requiring periodic electrical refresh. | 2018, 2021, 2023 |
| DAC Resolution | The smallest incremental analog output change corresponding to a 1-bit LSB input change. | 2016, 2019, 2022 |
| Quantization Error (eq) | The inherent mathematical uncertainty in A/D conversion, bounded by eq = VLSB / 2. | 2019, 2022 |
| Flash ADC | An ultra-fast ADC using 2^N - 1 parallel voltage comparators and a priority encoder to digitize analog signals in 1 clock cycle. | 2015, 2018, 2021, 2024 |
| Dual-Slope ADC | A high-precision ADC integrating input voltage Vin against reference Vref, producing counts N2 independent of R, C, or clock frequency. | 2016, 2020, 2023 |
2. Master Formula Reference Sheet
2.1 Flip-Flop Characteristic & Excitation Equations
| Flip-Flop | Char. Equation | Exc (00) | Exc (01) | Exc (10) | Exc (11) |
|---|---|---|---|---|---|
| SR | Qn+1 = S + R’Qn | S=0, R=X | S=1, R=0 | S=0, R=1 | S=X, R=0 |
| JK | Qn+1 = JQn’ + K’Qn | J=0, K=X | J=1, K=X | J=X, K=1 | J=X, K=0 |
| D | Qn+1 = D | D=0 | D=1 | D=0 | D=1 |
| T | Qn+1 = T Qn | T=0 | T=1 | T=1 | T=0 |
2.2 Counter & Timing Formulas
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Ripple Counter Cumulative Delay: ttotal = N tpd
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Ripple Counter Maximum Frequency: fmax = 1 / (N tpd)
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BJT Astable Frequency: f = 1 / (1.386 RC)
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IC 555 Astable HIGH Time: thigh = 0.693 (RA + RB) C
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IC 555 Astable LOW Time: tlow = 0.693 RB C
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IC 555 Astable Frequency: f = 1.44 / ((RA + 2 RB) C)
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IC 555 Astable Duty Cycle: D = ((RA + RB) / (RA + 2 RB)) 100%
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IC 555 Monostable Pulse Width: tW = 1.1 RA C
2.3 Memory, DAC & ADC Formulas
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Memory Capacity: Bits = 2^K M (Bytes = (2^K M) / 8)
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DAC Step Size (Resolution): VLSB = VFS / (2^N - 1)
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ADC Quantization Error: eq = VLSB / 2 = VFS / (2(2^N - 1))
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Flash ADC Comparators Required: Ncomp = 2^N - 1
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Dual-Slope ADC Conversion Count: N2 = (Vin / Vref) 2
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SAR ADC Conversion Time: Tconv = N Tclk