7.06 Semiconductor & Magnetic Memory Core Operations
In-depth analysis of semiconductor memory cell electronics (6T SRAM latches, 1T1C DRAM refresh dynamics, Flash floating gates) and magnetic core coincident-current selection (X-Y matrix, destructive read-out, restore cycle).
1. Semiconductor Memory Hierarchy & Comparison Matrix
| Memory Type | Cell Structure | Volatility | Refresh Needed | Relative Speed | Density |
|---|---|---|---|---|---|
| SRAM | Cross-coupled 6T MOSFET latch | Volatile | No | Extremely Fast (1-10 ns) | Low |
| DRAM | 1T MOSFET + 1 Storage Capacitor (1T1C) | Volatile | Yes (2-64 ms) | Fast (30-60 ns) | High |
| EPROM | Floating-Gate MOSFET (UV erased) | Non-Volatile | No | Fast Read / Slow Write | Medium |
| EEPROM | Floating-Gate MOSFET (Electrically erased) | Non-Volatile | No | Fast Read / Slow Write | Medium |
| Flash | Block-erasable Floating-Gate array | Non-Volatile | No | Fast Read / Block Write | High |
2. Magnetic Core Memory Read & Write Operations [PYQ: 2015–2025]
A magnetic core memory array uses toroidal ferrite cores woven with four distinct wires:
- X-Drive Wire: Carries +1/2Im or -1/2Im.
- Y-Drive Wire: Carries +1/2Im or -1/2Im.
- Sense Wire: Threaded through all cores in a plane to detect voltage pulses during Read.
- Inhibit Wire: Threaded parallel to Y-wires to prevent writing 1 when writing 0.
2.1 Operational Cycles
- Destructive Read: Apply -1/2Im to selected X and Y wires. Net field -Im flips core from 1 (+Br) to 0 (-Br), inducing a voltage pulse on the Sense wire.
- Write / Restore Cycle: Apply +1/2Im to X and Y. To write 0, apply -1/2Im to the Inhibit wire to cancel net field to +1/2Im < Im.