00 Chapter 7 Active-Recall Diagnostic Quiz (Multivibrators, Memory & Converters)
Overview: Test your conceptual understanding and exam readiness for multivibrators, 555 timers, RAM/ROM architectures, magnetic memory, DAC topologies, and ADC techniques.
Question 1: Multivibrator Stability States
How many stable and quasi-stable states exist in an Astable vs. Monostable vs. Bistable multivibrator?
Solution:
- Astable: 0 stable states, 2 quasi-stable states (free-running oscillator).
- Monostable: 1 stable state, 1 quasi-stable state (single pulse generator).
- Bistable: 2 stable states, 0 quasi-stable states (flip-flop memory cell).
Question 2: 555 Astable Frequency Formula
Write the frequency formula f for a 555 timer connected in astable mode with resistors R_A, R_B and capacitor C.
Solution:
f = 1.44 / ((R_A + 2 R_B) C)
Question 3: 555 Timer Duty Cycle Extension
Why does a standard 555 astable circuit always produce a duty cycle D > 50%, and how can an exact 50% duty cycle be achieved?
Solution:
Charging occurs through R_A + R_B, while discharging occurs only through R_B, making t_high > t_low (D = (R_A+R_B)/(R_A+2R_B) > 50%). To achieve D=50%, connect a steering diode in parallel with R_B so charging bypasses R_B directly through R_A.
Question 4: SRAM vs. DRAM Refresh Requirement
Why does DRAM require periodic electrical refresh cycles while SRAM does not?
Solution:
- DRAM: Stores charge on a tiny 1T1C MOS capacitor that leaks charge over time (2-64 ms), requiring periodic refresh cycles to restore charge.
- SRAM: Stores data in a cross-coupled 6-transistor (6T) flip-flop latch that holds state indefinitely as long as power is applied.
Question 5: EPROM vs. EEPROM Erasure
How is stored data erased in an EPROM vs. an EEPROM chip?
Solution:
- EPROM: Erased entirely by exposing the chip’s quartz window to Ultraviolet (UV) light for 20-30 minutes.
- EEPROM: Erased byte-by-byte or in sectors in-circuit using electrical voltage pulses.
Question 6: Magnetic Core Destructive Read
Why is a Read operation in magnetic core memory termed a “Destructive Read”?
Solution:
Reading is performed by applying drive currents that force the core to state 0. If the core stored a 1, the flux change induces a voltage pulse on the sense wire, but the state 1 is destroyed (reset to 0). A write/restore cycle must immediately follow to rewrite 1 back into the core.
Question 7: R-2R Ladder DAC Advantage
What is the primary manufacturing advantage of an R-2R Ladder DAC over a Binary Weighted-Resistor DAC?
Solution:
The weighted-resistor DAC requires N precision resistor values spanning a 2^(N-1):1 ratio, which is difficult to fabricate on an IC. The R-2R ladder requires only two resistor values (R and 2R), providing superior temperature tracking and ease of monolithic IC fabrication.
Question 8: ADC Quantization Error Bounds
What is the maximum quantization error e_q for an N-bit ADC with full-scale voltage V_FS?
Solution:
e_q = +/- V_LSB / 2 = +/- V_FS / (2(2^N - 1))
Question 9: Dual-Slope ADC Independence Proof
Why is the digital output count N_2 of a Dual-Slope Integrating ADC independent of component tolerances (R, C) and clock frequency?
Solution:
Integrator peak voltage during run-up is V_peak = (V_in * T_1) / (R * C). Run-down time T_2 to return to 0 V is V_peak = (V_ref * T_2) / (R * C). Equating both gives V_in * T_1 = V_ref * T_2 ⇒ N_2 = (V_in / V_ref) * 2^n. The terms R, C, and clock period T_clk cancel out completely!
Question 10: Flash ADC Hardware Explosion
How many parallel voltage comparators are required to construct an 8-bit Flash ADC?
Solution:
Comparators = 2^N - 1 = 2^8 - 1 = 256 - 1 = 255 comparators